Abstract—This paper considers the viability of compact low-resolution low-power mini digital-to-analog converters (mini-DACs) for use in large arrays of neural type cells, where programmable weights are required. Transistors are biased in weak inversion in order to yield small currents and low power consumptions, a necessity when building large size arrays. One important drawback of weak inversion operation is poor matching between transistors. The resulting effective precision of a fabricated array of 50 DACs turned out to be 47 % (1.1 bits), due to transistor mismatch. However, it is possible to combine them two by two in order to build calibrated DACs, thus compensating for inter-DAC mismatch. It is shown experimentally that the precision can be improved easily by a factor of 10 (4.8 % or 4.4 bits), which makes these DACs viable for low-resolution applications such as massive arrays of neural processing circuits. A design methodology is provided, and illustrated through examples, to obtain calibrated mini-DACs of a given target precision. As an example application, we show simulation results of using this technique to calibrate an array of digitally controlled integrate-and-fire neurons. Index Terms—Analog design, calibration, current splitters, digital-to-analog converters, fuzzy circuits, neural networks, subthreshold, weak inversion. I.

We describe a formalism for quantifying the performance of spike-based winner-take-all (WTA) VLSI chips. The WTA function non-linearly amplifies the output responses of pixels/neurons dependent on the input magnitudes in a decision or selection task. In this work, we show a theoretical description of this winner-take-all computation which takes into consideration the input statistics, neuron response variance, and output rates. This analysis is tested on a spiking VLSI neuronal network fabricated in a 4-metal, 2-poly 0.35 µm CMOS process. The measured results of the winner-take-all performance from this chip correspond to the theoretical prediction. This formalism can be applied to any implementation of spike-based neurons.

A new five-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation regions, including short-channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch 1 into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short-channel transistors. Index Terms--- Analog circuit modeling, analog circuit simulation, analog VLSI design, mismatch modeling, transistor mismatch, transistor modeling.. I. INTRODUCTION C HARACTERIZATION and simulation of MOS transistor mismatch is crucial for precision analog design. Mismatch models include two terms: 1) a size dependent and 2) a distance dependent term [1]. The distance dependent term can...

A five parameter mismatch model continuos from weak to strong inversion is presented. The model is an extension of a previously reported one valid in the strong inversion region [1]. A mismatch characterization of NMOS and PMOS transistors for 30 different geometries has been done with this continuos model. The model is able to predict current mismatch with a mean relative error of 13.5 % in the weak inversion region and 5 % in strong inversion. This is verified for 12 different curves, sweeping V G, V DS and V S. 1.

State dependent computation using coupled recurrent networks ∗