It was recently observed that, in order to improve the defect coverage of a test set, test generation based on fault models such as the single-line stuck-at model may need to be augmented so as to derive test sets that detect each modeled fault more than once. In this work, we report on test pattern generators for combinational circuits that generate test sets to detect each single line stuck-at fault a given number of times. Additionally, we study the effects of test set compaction on the defect coverage of such test sets. For the purpose of experimentation, defect coverage is measured by the coverage of surrogate faults, using a framework proposed earlier. Within this framework, we show that the defect coverage does not have to be sacrificed by test compaction if the test set is computed using appropriate test generation objectives. Moreover, two test sets generated using the same test generation objectives, except that compaction heuristics were used during the generation of one but not the other, typically have similar defect coverages, even if the compacted test set is significantly smaller than the noncompacted one. Test generation procedures and experimental results to support these claims are presented.

Hierarchy can be used to make compiler-driven logic simulation available for very large circuits where the size of a flat simulation routine is too big. But due to many parameter evaluations, hierarchical simulators have an unacceptable runtime. In this paper, it is shown how to reach the performance of a flat simulator using hierarchical code but avoiding the expensive information transport with parameters. Introduction Many logic simulators are event-driven [AS87, BHKS91]. This means that they only calculate the assignment of a signal when it could have changed. Unfortunately, the management of such an event is more expensive than the calculation of many signal assignments. So, event checks are not always better than brute force assignment calculation -- depending on the structure of the circuit and the simulated input pattern. If, for each circuit considered, a simulation routine is created and compiled to speed up the expensive simulation, it is called compiler-driven simulation....

In this paper, three demands of a good logic simulator for hierarchical circuits are postulated: stack oriented signal assignment, hierarchical circuit representation and linear runtime. It is shown that the intuitive idea of a hierarchical simulator does not hold condition 3 having a runtime of \Theta(n 2 ) in the circuit size. May this be improved or is there a contradiction in these conditions? Not in the way that there are two conflicting groups, as for each pair of these conditions an algorithm may be presented. But it is shown that there is no way to fulfill all of them at once! Introduction To deal with complex systems, hierarchical representations are often needed. They shorten memory usage and allow single computation for several instances of the same object. So hierarchy might be such a sweat thing if it had not such a big disadvantage compared to flat representations: the hierarchy borders separate objects and may result in expensive information transports. A way to avoid...