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A 3.3V Single-Poly CMOS Audio ADC Delta-Sigma Modulator with 98dB Peak SINAD and 105dB Peak SFDR
- IEEE J. Solid-State Circuits
, 2000
"... This paper presents a second-order ## modulator for audio-band A#D conversion implemented in a 3.3V, 0.5#m, single-poly CMOS process using metal-metal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a low-complexity #rst-order mismatch-shaping 33-level DAC and a 33-leve ..."
Abstract
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Cited by 16 (11 self)
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This paper presents a second-order ## modulator for audio-band A#D conversion implemented in a 3.3V, 0.5#m, single-poly CMOS process using metal-metal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a low-complexity #rst-order mismatch-shaping 33-level DAC and a 33-level #ash ADC with digital common-mode rejection and dynamic element matching of comparator o#sets. These signal processing innovations, combined with established circuit techniques, enable state of the art performance in CMOS technology optimized for digital circuits. I. Introduction For mixed-signal ICs with high digital circuit content, single-poly CMOS optimized for digital circuits can provide the lowest overall implementation cost. For example, it is preferable to avoid the expense of double-poly capacitors, thick-oxide transistors for 5V operation, or other analog process enhancements when analog circuits such as data converters make up only a small portion of the total die area. This ...
Advanced Analog Electronics Term Report Prepared by: Class Instructor
, 2001
"... Currently, there is an ever-growing demand for low-power mixed signal integrated circuits for such applications as mobile or wired communications and other portable systems. In these applications, the supply voltage is being scaled down to reduce overall power consumption. As for the fabrication pro ..."
Abstract
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Currently, there is an ever-growing demand for low-power mixed signal integrated circuits for such applications as mobile or wired communications and other portable systems. In these applications, the supply voltage is being scaled down to reduce overall power consumption. As for the fabrication process, digital CMOS is always the preferred technology due to its efficient economic costs. As a result, contemporary analog circuits must not only operate with low supply voltages, but should also be realizable in typical digital CMOS processes. However, this concession leads to significant performance degradation of the analog circuits. Since op amps are the most critical building blocks in all analog systems, the objective of this report is to study the theory and design of low voltage op amps for digital CMOS processes. Two categories of low voltage op amps have been identified as being suitable for low voltage applications [1]. The first category operates with 2-3V power supplies. The distinct features of this class of op amps are that they utilize N-P complementary, input pairs and the gain stages use active gain enhancement to boost the gain of the overall

