This paper presents a second-order ## modulator for audio-band A#D conversion implemented in a 3.3V, 0.5#m, single-poly CMOS process using metal-metal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a low-complexity #rst-order mismatch-shaping 33-level DAC and a 33-level #ash ADC with digital common-mode rejection and dynamic element matching of comparator o#sets. These signal processing innovations, combined with established circuit techniques, enable state of the art performance in CMOS technology optimized for digital circuits. I. Introduction For mixed-signal ICs with high digital circuit content, single-poly CMOS optimized for digital circuits can provide the lowest overall implementation cost. For example, it is preferable to avoid the expense of double-poly capacitors, thick-oxide transistors for 5V operation, or other analog process enhancements when analog circuits such as data converters make up only a small portion of the total die area. This ...

Mismatch-shaping digital-to-analog converters (DACs) have become widely used in high-performance delta-sigma data converters because they facilitate delta-sigma modulators with multibit quantization. Relative to single-bit quantization, multibit quantization significantly relaxes the analog circuit performance necessary to achieve a given level of data converter precision, but significant digital logic is required to perform the mismatch shaping. In modern very large scale integration processes optimized for digital circuitry, this tends to be a good tradeoff in terms of both area and power consumption. It is nonetheless desirable to minimize the digital complexity as much as possible. Moreover, in delta--sigma analog-to-digital converters the mismatch-shaping logic is in the feedback path of the delta-sigma modulator, so it is essential to maintain a sufficiently small propagation delay through the mismatch-shaping logic. This paper presents and analyzes several variations of the switching blocks within a tree-structured mismatch-shaping DAC that result in the most hardware-efficient first-order and second-order mismatch -shaping DAC implementations yet known to the authors. The variations presented allow designers to tradeoff complexity for propagation-delay reduction so as to tailor designs to specific applications.

This paper presents a di#erential input #ash ADC with digital common mode rejection #DCMR# and dithered, noise shaped requantization used in a high-performance, single-poly CMOS ADC ## modulator IC. By avoiding the use of metal-metal capacitors, the DCMR #ash ADC required 14# less area than a switched-capacitor implementation and avoided circuit implementation problems. Measurements and analysis show that the DCMR #ash ADC rejects common mode noise without generating spurious tones. In the absence of common mode noise, its quantization noise power is equivalent to a conventional #ash ADC. I. INTRODUCTION The availability of mismatch-shaping multibit DACs has helped to make the implementation of high-resolution multibit ##ADCs feasible. Compared to a single-bit design, a multibit ## modulator can achieve the same signal to quantization noise performance with a lower modulator order and lower oversampling ratio #OSR#. The use of multibit feedback also relaxes the slew rate and settling...