In the last three decades a considerable amount of research has been pursued in the efficient implementation of the pending event set (PES) associated with discrete-event simulation. The reason is simple: a fast event management has a very crucial impact in the total running time of both sequential and parallel simulations. This report focuses on this problem by studying the empirical performance of a number of solutions to the PES implementation in which we include a complete binary tree described in [26], 1 Introduction The PES is defined as the set of all the events generated during a discrete-event simulation and whose occurrence have not been simulated yet. In order to determine the next event to take place, it is necessary to extract the event with the least time from the PES. We call this operation extract-min. On the other hand, the occurrence of any event during the simulation can produce the insertion of new pending or future events in the PES; insert operation. These two b...

this paper we study the performance of the very first tournament based complete binary tree. We focus on discrete-event simulation and our results show that this unknown predecessor of heaps can be a more efficient alternative to the fastest pending event set implementations reported in the literature. We also extend the idea of binary tournaments to a (2; L)-tournament structure which exhibits the property of delaying the processing of events with larger timestamps whilst it keeps similar theoretical performance bounds to the native (2; 1)-structure or CBT. This property can be certainly useful in systems where many pending events are expected to be deleted or rescheduled during the simulation. 2 Tournament trees

In hardware design of today, there is a growing usage of hardware design languages to speed up the time-to-market. As the design complexity grows, so does the simulation time. To solve this problem, several research groups have suggested the use of parallel computers to speed up simulation. This report surveys some of the issues involved when designing a parallel simulator for one of the more popular hardware description languages, VHDL. The report includes a brief survey of VHDL itself, as well as a survey of simulation methodologies, especially parallel discrete event simulation. Some important issues when designing a parallel VHDL simulator are addressed and some parallel VHDL simulation projects and experiments that already have been initiated are described briefly. The report concludes with some general remarks on important research that needs to be done as well as suggesting a suitable approach for future research. Keywords: hardware description languages, VHDL, simul...