research relevant to the design and application of high performance scientific computers. We test our ideas by designing, building, and using real systems. The systems we build are research prototypes; they are not intended to become products. There two other research laboratories located in Palo Alto, the Network Systems

There is a growing interest in optimizations that depend on or benefit from an execution profile that tells where time is spent. How well does a profile from one run describe the behavior of a different run, and how does this compare with the behavior predicted statically by examining the program itself ? This paper defines two abstract measures of how well a profile predicts actual behavior. According to these measures, real profiles indeed do better than estimated profiles, usually. A perfect profile from an earlier run with the same data set, however, does better still, sometimes by a factor of two. Using such a profile is unrealistic, and can lead to inflated expectations of a profile-driven optimization. i 1. Introduction Many people have built or speculated on systems that use a run-time profile to guide code optimization. Applications include the selection of variables to promote to registers [7,8], placement of code sequences to improve cache behavior [3,6], and pre...

This paper investigates issues involving writes and caches. First, tradeoffs between write-through and write-back caching when writes hit in a cache are considered. A mixture of these two alternatives, called write caching is proposed. Write caching places a small fully-associative cache behind a write-through cache. A write cache can eliminate almost as much write traffic as a write-back cache. Second, tradeoffs on writes that miss in the cache are investigated. In particular, whether the missed cache block is fetched on a write miss, whether the missed cache block is allocated in the cache, and whether the cache line accessed is invalidated are considered. Depending on the combination of these polices chosen, the entire cache miss rate can vary by a factor of two on some applications. Furthermore, the combination of no-fetch-on-write and write-allocate can provide better performance than cache line allocation instructions. Finally, the traffic at the back side of write-through and wr...

The behavior of the TCP protocol in simple situations is well-understood, but when multiple connections share a set of network resources the protocol can exhibit surprising phenomena. Earlier studies have identified several such phenomena, and have analyzed them using simulation or observation of contrived situations. This paper shows how, by analyzing traces of a busy segment of the Internet, it is possible to observe these phenomena in "real life" and measure both their frequency and their effects on performance. A TCP implementation might use similar techniques to support rate-based congestion control.

research relevant to the design and application of high performance scientific computers. We test our ideas by designing, building, and using real systems. The systems we build are research prototypes; they are not intended to become products. There is a second research laboratory located in Palo Alto, the Systems Research Center (SRC). Other Digital research groups are located in Paris (PRL) and in Cambridge,

The results of an experimental investigation of pool boiling of water at subatmospheric pressures from small horizontal heat sources are reported. The heat sources are upward-facing copper surfaces submerged in a laterally-confined, finite pool of liquid. The saturated pool boiling heat transfer characteristics and the critical heat flux (CHF) condition were determined in the experiments. Low pressure boiling of saturated water provides a means of removing heat at high heat flux levels while maintaining low surface temperatures. However, at heat flux levels up to about 60 2 W/cm the frequency of bubble departure at low pressure is much less than the frequency of bubble departure at higher pressure (atmospheric). With low pressure boiling, only one or two very large bubbles form cyclically on the small heated surface, during the boiling process. This intermittent process may result in large, undesirable temperature oscillations at the heated surface for low pressure boiling. High-frequ...

Recent developments in computer-aided design have enabled highly automated layout of custom ECL circuits. These layouts have a much higher circuit and power density than gate array designs. It is now possible to place an entire ECL microprocessor, including floating point unit and cache memory, on one large die. To demonstrate the capability of supporting such a die, we built and tested low-cost, air-cooled single-chip packaging for a 12.6 mm x 15.4 mm die. Our PPGA package supplied the required current and maintained junction temperatures at less than 100° C while dissipating 150 W. This required innovation in five areas: die metalization, bondwire layout, PPGA package design, die attach, and cooling by a thermosiphon. This is a preprint of a paper that will be presented at the nd 42 Electronic Components and Technology Conference, San Diego, Caifornia, May, 18-20, 1992. Copyright Ó 1992 IEEE i ii Table of Contents Nomenclature vii 1. Introduction 1 2. Die Metalization 4 3. Bo...

This study considers boiling binary mixtures of water with methanol or 2-propanol at subatmospheric pressures. Liquid-phase equilibrium vapor pressures, binary phase equilibrium thermodynamic properties, heat transfer characteristics, and the critical heat flux (CHF) condition are determined for saturated pool boiling from a localized heat source while varying the concentrations of methanol and 2-propanol in water. The heat source is an upward-facing copper surface submerged in a laterally-confined, finite pool. Low pressure boiling of aqueous mixtures provides a means of removing high heat fluxes while maintaining low surface temperatures. Small additions of alcohol to water increase the CHF condition above that of pure water. Higher concentrations of alcohol begin decreasing the CHF condition to that of the pure alcohol. While single-component correlations using mole weighted binary liquid thermodynamic properties have been shown to predict ideal binary mixture boiling behavior, they...

Rsim is a switch-level simulator which can simulate large digital MOS integrated circuits with speedups of over 3 orders of magnitude over SPICE. Unfortunately, Rsim's simple switched-resistor model renders it incapable of simulating certain CMOS and most BiCMOS and ECL digital circuits. We observe that the switched-resistor model is just one particular piecewise linear model and that Rsim's simulation framework can accommodate more elaborate piecewise linear models. The resulting simulator, Mom, combines the efficiency of switch-level simulation with the ability to simulate a wider variety of circuits. We demonstrate Mom's efficiency and flexibility on a variety of circuits. This research was supported in part by DARPA contract N00039-91-C-1038. d i g i t a l Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA 1 Introduction The high cost of semiconductor processing makes it desirable to verify the correctness of a large custom digital integr...

This report is the technical reference for the T1D4PKT adapter, a communication option module for TurboChannel I/O systems. It uses basic HDLC (flags, bitstuffing, CRC) to send and receive packets over a T1 circuit with D4 framing (1.544 Mb/s digital telephone circuit). The adapter was designed for use in packet switching routers linking local area networks into metropolitan-area and wide-area networks. This adapter is a research prototype; it is not a product. Copyright 1991 Digital Equipment Corporation d i g i t a l Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA TurboChannel T1 Adapter 1. Overview The T1D4PKT adapter is a communication option module for TurboChannel I/O systems. It uses basic HDLC (flags, bit-stuffing, CRC) to send and receive packets over a T1 circuit with D4 framing (1.544 Mb/s digital telephone circuit). The adapter was designed for use in packet switching routers linking local area networks into metropolitan-area and wi...