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Speeding Up HMM Decoding and Training by Exploiting Sequence Repetitions
"... We present a method to speed up the dynamic program algorithms used for solving the HMM decoding and training problems for discrete timeindependent HMMs. We discuss the application of our method to Viterbi’s decoding and training algorithms [33], as well as to the forwardbackward and BaumWelch [ ..."
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Cited by 11 (5 self)
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We present a method to speed up the dynamic program algorithms used for solving the HMM decoding and training problems for discrete timeindependent HMMs. We discuss the application of our method to Viterbi’s decoding and training algorithms [33], as well as to the forwardbackward and BaumWelch [6] algorithms. Our approach is based on identifying repeated substrings in the observed input sequence. Initially, we show how to exploit repetitions of all sufficiently small substrings (this is similar to the Four Russians method). Then, we describe four algorithms based alternatively on run length encoding (RLE), LempelZiv (LZ78) parsing, grammarbased compression (SLP), and byte pair encoding (BPE). Compared to Viterbi’s algorithm, we achieve speedups of Θ(log n) using the Four Russians method, Ω ( r log n r) using RLE, Ω ( ) using LZ78, Ω ( ) using SLP, and Ω(r) using BPE, where k is the number log r k k of hidden states, n is the length of the observed sequence and r is its compression ratio (under each compression scheme). Our experimental results demonstrate that our new algorithms are indeed faster in practice. Furthermore, unlike Viterbi’s algorithm, our algorithms are highly parallelizable.
Pipelined Architectures For The Viterbi Algorithm
, 1997
"... The main part of the Viterbi Algorithm is a nonlinear feedback loop which presents a bottleneck for highspeed implementations. We propose four different solutions for increasing the computation speed of the Viterbi Algorithm, three of them are based on the utilization of pipelined systems combined ..."
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Cited by 1 (0 self)
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The main part of the Viterbi Algorithm is a nonlinear feedback loop which presents a bottleneck for highspeed implementations. We propose four different solutions for increasing the computation speed of the Viterbi Algorithm, three of them are based on the utilization of pipelined systems combined with efficient scheduling methodologies and the other one is based on the simplification of the ACS recursion to cut down the critical path of the system. 1. INTRODUCTION The Viterbi Algorithm [1] is widely employed in communications and image compression. For a given data sequence, the Viterbi algorithm is used to find the most likely value in a weighted branches graph (trellis). This graph corresponds to the transition diagram of a convolutional encoder. A trellis is a representation where the states in instant t are connected to those in instant t 1 by branches that specify state transitions. Each transition has an associated branch metric (BM) that is a measure of the unlikelihood of th...
HighSpeed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining
, 1996
"... The main part of the Viterbi Algorithm is a nonlinear feedback loop which presents a bottleneck for highspeed implementations. In this paper we present a novel scheduling scheme that allows to dramatically increase the available speed of the system. This is done through the utilization of lookahea ..."
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Cited by 1 (1 self)
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The main part of the Viterbi Algorithm is a nonlinear feedback loop which presents a bottleneck for highspeed implementations. In this paper we present a novel scheduling scheme that allows to dramatically increase the available speed of the system. This is done through the utilization of lookahead techniques to compute non sequential data and, in this way, break the recursivity of the algorithm. This permits introducing and exploiting the pipelining in an efficient way. The formal model developed is employed for the scheduling of the computations among the processors in order to obtain a 100% pipelining stage utilization. As a result, we obtain a speed growth comparable to previous parallel solutions, but without their important area growth. 1 INTRODUCTION The Viterbi algorithm [1] is known to be an efficient method for the realization of maximum likelihood decoding of convolutional codes, maximum likelihood estimation of Trellis Coded Modulation (TCM) and Trellis Coded Quantiza...
Accelerating Dynamic Programming
, 2009
"... Dynamic Programming (DP) is a fundamental problemsolving technique that has been widely used for solving a broad range of search and optimization problems. While DP can be invoked when more specialized methods fail, this generality often incurs a cost in efficiency. We explore a unifying toolkit fo ..."
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Cited by 1 (0 self)
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Dynamic Programming (DP) is a fundamental problemsolving technique that has been widely used for solving a broad range of search and optimization problems. While DP can be invoked when more specialized methods fail, this generality often incurs a cost in efficiency. We explore a unifying toolkit for speeding up DP, and algorithms that use DP as subroutines. Our methods and results can be summarized as follows. – Acceleration via Compression. Compression is traditionally used to efficiently store data. We use compression in order to identify repeats in the table that imply a redundant computation. Utilizing these repeats requires a new DP, and often different DPs for different compression schemes. We present the first provable speedup of the celebrated Viterbi algorithm (1967) that is used for the decoding and training of Hidden Markov Models (HMMs). Our speedup relies on the compression of the HMM’s observable sequence. – Totally Monotone Matrices. It is well known that a wide variety of DPs can be reduced to the problem of finding row minima in totally monotone matrices. We introduce this scheme in the context of planar graph problems. In particular, we show that planar graph problems
An Area Reduced Radix4 Viterbi Decoder Design *
"... Abstract – The Viterbi decoder is a crucial component for successful modern communication systems. In this paper, we propose an area reduced, high speed Viterbi decoder based on the radix4 architecture. The area is reduced by rearranging the ACS operations, and the speed is improved by retiming. Th ..."
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Abstract – The Viterbi decoder is a crucial component for successful modern communication systems. In this paper, we propose an area reduced, high speed Viterbi decoder based on the radix4 architecture. The area is reduced by rearranging the ACS operations, and the speed is improved by retiming. The areatime product of the proposed design is improved by 11 % compared to that of the previous high speed radix4 architecture.
HighSpeed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining
, 1996
"... The main part of the Viterbi Algorithm is a nonlinear feedback loop which presents a bottleneck for highspeed implementations. In this paper we present a novel scheduling scheme that allows to dramatically increase the available speed of the system. This is done through the utilization of lookahea ..."
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The main part of the Viterbi Algorithm is a nonlinear feedback loop which presents a bottleneck for highspeed implementations. In this paper we present a novel scheduling scheme that allows to dramatically increase the available speed of the system. This is done through the utilization of lookahead techniques to compute non sequential data and, in this way, break the recursivity of the algorithm. This permits introducing and exploiting the pipelining in an efficient way. The formal model developed is employed for the scheduling of the computations among the processors in order to obtain a 100% pipelining stage utilization. As a result, we obtain a speed growth comparable to previous parallel solutions, but without their important area growth. 1 INTRODUCTION The Viterbi algorithm [1] is known to be an efficient method for the realization of maximum likelihood decoding of convolutional codes, maximum likelihood estimation of Trellis Coded Modulation (TCM) and Trellis Coded Quantiza...
Analysis of Convolutional Encoders and Synthesis of Rate2/n Viterbi Decoders
"... In this paper the problem of obtaining efficient hardware for Viterbi decoders for high rate convolutional encoders is addressed. It is first shown that the graphs describing the interconnection of the addcompareselect units required may be classified in terms of structures of which there are only ..."
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In this paper the problem of obtaining efficient hardware for Viterbi decoders for high rate convolutional encoders is addressed. It is first shown that the graphs describing the interconnection of the addcompareselect units required may be classified in terms of structures of which there are only a small number for a given code constraint length. They correspond to the assignment of individual register lengths in the ensemble of shift registers in the feedforward encoder. The structures relate to the partitioning of the states such that common successors are grouped together and successive partitioning leads to a hierarchical, modular VLSI layout method. Example symbolic grid layouts are given for 16 and 64 state codes. It is noted that within a given structure, the parity check matrices map into local wiring patterns implying a method for implementing classuniversal programmable or adaptive decoders.
ALGEBRAIC SURVIVOR MEMORY MANAGEMENT FOR VlTERBl DETECTORS
"... The problem of survivor memory management of a Viterbi detector is classically solved either by a registerexchange implementation which has minimal latency, but large hardware complexity and power consumption, or by a traceback scheme with small power consumption, but larger latency. Here an algebra ..."
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The problem of survivor memory management of a Viterbi detector is classically solved either by a registerexchange implementation which has minimal latency, but large hardware complexity and power consumption, or by a traceback scheme with small power consumption, but larger latency. Here an algebraic formulation of the survivor memory management is introduced which provides a framework for the derivation of new algorithmic and architectural solutions. VLSI case studies of specific new solutions show that more than 50 % savings are possible in hardware complexity as well as power consumption. 1
Low Power UWB Transceiver Design Using Dynamic Voltage Scaling
, 2007
"... Low power consumption is a critical issue in many UWB systems. This paper investigates the application of dynamic voltage scaling DVS and other low power design techniques to a multibandOFDM UWB transceiver baseband circuit design in order to reduce average power consumption of the ship. The result ..."
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Low power consumption is a critical issue in many UWB systems. This paper investigates the application of dynamic voltage scaling DVS and other low power design techniques to a multibandOFDM UWB transceiver baseband circuit design in order to reduce average power consumption of the ship. The results show significant power savings over the conventional approach.