Compressed digital video is one of the most important traffic types in future integrated services networks. However, a network service that supports delay-sensitive video imposes many problems since compressed video sources are variable bit rate (VBR) with a high degree of burstiness. In this paper, we consider a network service that can provide deterministic guarantees on the minimum throughput and the maximum delay of VBR video traffic. A common belief is that due to the burstiness of VBR traffic, such a service will not be efficient and will necessarily result in low network utilization. We investigate the fundamental limits and tradeoffs in providing deterministic performance guarantees to video and use a set of 10 to 90 minute long MPEG-compressed video traces for evaluation. Contrary to conventional wisdom, we are able to show that, in many cases, a deterministic service can be provided to video traffic while maintaining a reasonable level of network utilization. We first conside...

In this paper we present algorithms for flow admission control at an EDF link scheduler when the flows are characterized by peak rate, average rate and burst size. We show that the algorithms have very low computational complexity and are easily applicable in practice. The complexity can be further decreased by introducing the notion of flex classes. We evaluate the penalty in efficiency that the classes incur to the EDF scheduler. We find that this efficiency degradation can be made arbitrarily small and is acceptable even for a small number of classes.

Complex real-time systems require jointly schedule both periodic task and aperiodic tasks with hard and soft deadlines. This problem has been subject of considerably research in real-time systems and one of the most widely accepted solutions are dynamic slack stealing algorithms (DSS) for scheduling aperiodic tasks, running with earliest deadline first (EDF) algorithms for scheduling periodic ones. However, these algorithms are rather impractical, since they all imply a considerably scheduling overhead that always results in delays and reduced CPU utilization. One of the proposed solutions to this problem is doing scheduling in hardware. This paper follows this approach and analyzes in depth a hardware design based on binary trees. The proposed solution is a circuit that behaves as a sort of sophisticated interrupt controller whose inputs are the task workload and the interrupts, and whose output interrupts the CPU exclusively when a task switch should occur, providing the identifier of the task to be resumed (the highest priority task).