Manisha Pattanaik, “A Novel Approach to Reduce the Gate and Sub-threshold Leakage in a conventional SRAM Bit-cell Structure at Deep-Sub Micron CMOS (0)

by R K Singh Shukla
Venue:2011 [4] Sung-Mo (Steve) Kang, Yusuf Leblebici, “CMOS Digital Integrated Circuits-Analysis and Design”, Third Edition Tata McGraw-Hill Edition