The technology to build highly integrated 3-dimensional computational image sensors by stacking and interconnecting layers of 2-dimensional silicon ICs is being developed. Unlike multi-chip module (MCM-V) packaging, in which interconnect lines are brought to the periphery of a chip stack to achieve vertical integration, this new technology allows virtually unrestricted placement of vertical vias within the interior of the chip. The goal of this development is to enable high speed, high resolution image processing in compact low power wearable systems that would be coupled with a head-mounted display (HMD). Potential applications for these systems include target tracking and image stabilization. In this talk we focus on the architecture of the 3D image sensor, which includes pixel-parallel analog-to-digital conversion and programmable digital processors for pixel and block operations. We show that 3D technology will allow at least an order of magnitude decrease in power dissipation over...

Abstract—The quantification of substrate noise is an important issue in mixed-signal designs, where sensitive analog circuits are embedded in a hostile digital environment. In this paper we present an experimental environment to characterize the sensitivity of embedded analog circuits to digitally generated substrate noise. Our measurement technique is based on equivalent-time substrate voltage sampling and uses a simple differential latch comparator without explicit input sample-and-hold. A surprisingly large measurement bandwidth is observed, which is explained from the detailed circuit behavior. On our 0.18- m CMOS test chip, we have demonstrated that our system allows to wavetrace pulses as narrow as 200 ps accurately. Additionally, the extraction of precise measurement data from observations that are excessively corrupted by additive noise and timing jitter is addressed. We present simple yet very effective methods to accurately reconstruct pulse waveform features without the use of delicate deconvolution operations. Index Terms—CMOS integrated circuits, differential amplifiers, integrated circuit noise, jitter. I.

A 5V DS-CDMA correlator uses sampled analog signal processing to achieve 75mW power dissipation, 128MS/s processing rate and 54dB input dynamic range in a 1.2um CMOS process. A new passive correlation technique eliminates the integrating opamp and associated power and settling time overhead. Six 64-chip correlators recover the 2Mb/s data stream from the doubly modulated (PN & Walsh) I & Q input signals. A 10bit 8MS/s ADC digitizes the outputs of the correlators for subsequent digital data processing and acquisition /tracking control.

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Oversampled analog-to-digital (A/D) conversion based on sigma-delta (SD) modulation has gained increasing popularity. By sampling much faster than the Nyquist rate, oversampled converters can take advantage of available speed and exchange resolution in time for resolution in amplitude. SD modulation provides a noise shaping property that permits the use of coarse quantization only requiring robust components which are largely insensitive to component mismatch. These characteristics are well suited for VLSI technology and allow SD converters to be integrated on the same chip with digital signal processing circuitry. This is desirable because system integration increases and employing a single technology, which does not require high precision elements, is economically attractive. At the present time the dominant method of implementing SD modulators is the switchedcapacitor technique. This technique requires linear capacitors which are not necessary in digital technologies. In the last fe...

We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the channel equalization problem commonly encountered in digital communications. We show that, with the help of a slow but accurate ADC, the proposed code-domain adaptive finite-impulse-response filter is sufficient to remove the effect of component errors including capacitor mismatch, finite op-amp gain, op-amp offset, and sampling-switch-induced offset, provided they are not signal-dependent. The algorithm is all digital, fully adaptive, data-driven, and operates in the background. Strong tradeoffs between accuracy and speed of pipelined ADCs are greatly relaxed in this approach with the aid of digital correction techniques. Analog precision problems are translated into the complexity of digital signal-processing circuits, allowing this approach to benefit from CMOS device scaling in contrast to most conventional correction techniques.

Abstract—A pipelined ADC incorporates a digital foreground calibration technique that corrects errors due to capacitor mismatch, gain error, and op amp nonlinearity. Employing a highspeed, low-power op amp topology and an accurate on-chip resistor ladder and designed in 90-nm CMOS technology, the ADC achieves a DNL of 0.4 LSB and an INL of 1 LSB. The prototype digitizes a 233-MHz input with 53-dB SNDR while consuming 55 mW from a 1.2-V supply. Index Terms—Calibration by inverse function, foreground digital calibration, low gain op amp, nonlinearity correction, pipelined analog-to-digital converter, resistor-ladder DAC. I.

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