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25
Analogtodigital converter survey and analysis
 IEEE Journal on Selected Areas in Communications
, 1999
"... Abstract—Analogtodigital converters (ADC’s) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the stateoftheart of ADC’s, including experimental converters and commercially available parts. The distribution of resolution versus samplin ..."
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Cited by 134 (0 self)
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Abstract—Analogtodigital converters (ADC’s) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the stateoftheart of ADC’s, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Ms/s), resolution appears to be limited by thermal noise. At sampling rates ranging from 2 Ms/s to 4 giga samples per second (Gs/s), resolution falls off by 1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADC’s operating at multiGs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The recent trend toward singlechip ADC’s brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only 1.5 bits for any given sampling frequency over the last six–eight years. Index Terms—Analogtodigital converters, aperture jitter, comparator ambiguity, inputreferred noise, signaltonoise ratio, spuriousfree dynamic range. I.
A 1.8V digitalaudio sigmadelta modulator in 0.8µm CMOS
 IEEE Journal of SolidState Circuits
, 1997
"... Abstract — Oversampling techniques based on sigmadelta (ΣΔ) modulation offer numerous advantages for the realization of highresolution analogtodigital (A/D) converters in a lowvoltage environment. This paper examines the design and implementation of a CMOS ΣΔ modulator for digitalaudio A/D con ..."
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Cited by 21 (0 self)
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Abstract — Oversampling techniques based on sigmadelta (ΣΔ) modulation offer numerous advantages for the realization of highresolution analogtodigital (A/D) converters in a lowvoltage environment. This paper examines the design and implementation of a CMOS ΣΔ modulator for digitalaudio A/D conversion that operates from a single 1.8V power supply. A cascaded modulator that maintains a large fullscale input range while avoiding signal clipping at internal nodes is introduced. The experimental modulator has been designed with fullydifferential switchedcapacitor integrators employing different input and output commonmode levels and boosted clock drivers in order to facilitate low voltage operation. Precise control of commonmode levels, high power supply noise rejection, and low power dissipation are obtained through the use of twostage, class A/AB operational amplifiers. At a sampling rate of 4 MHz and an oversampling ratio of 80, an implementation of the modulator in a 0.8μm CMOS technology with metaltopolycide capacitors and NMOS and PMOS threshold voltages of +0.65V and –0.75V, respectively, achieves a dynamic range of 99 dB at a Nyquist conversion rate of 50 kHz. The modulator can operate from supply voltages ranging from 1.5 V to 2.5 V, occupies an active area of 1.5 mm 2, and dissipates 2.5 mW from a 1.8V supply.
A threeaxis micromachined accelerometer with a CMOS positionsense interface and digital offsettrim electronics
 IEEE Journal of SolidState Circuits
, 1999
"... Abstract — This paper describes a threeaxis accelerometer implemented in a surfacemicromachining technology with integrated CMOS. The accelerometer measures changes in a capacitive halfbridge to detect deflections of a proof mass, which result from acceleration input. The halfbridge is connected ..."
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Cited by 19 (3 self)
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Abstract — This paper describes a threeaxis accelerometer implemented in a surfacemicromachining technology with integrated CMOS. The accelerometer measures changes in a capacitive halfbridge to detect deflections of a proof mass, which result from acceleration input. The halfbridge is connected to a fully differential positionsense interface, the output of which is used for onebit force feedback. By enclosing the proof mass in a onebit feedback loop, simultaneous force balancing and analogtodigital conversion are achieved. Onchip digital offsettrim electronics enable compensation of random offset in the electronic interface. Analytical performance calculations are shown to accurately model device behavior. The fabricated singlechip accelerometer measures 4 2 4mm P, draws 27 mA from a 5V supply, and has a dynamic range of 84, 81, and 70 dB along the �, �, and �axes, respectively. Index Terms—Accelerometer, calibration, force balance, microelectromechanical systems (MEMS), sensor, sigma–delta.
A 12bit 75MS/s pipelined ADC using openloop residue amplification
 IEEE J. SolidState Circuits
, 2003
"... Abstract—Precision amplifiers dominate the power dissipation in most highspeed pipelined analogtodigital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple powerefficient openloop stages. In the multibit first ..."
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Cited by 15 (0 self)
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Abstract—Precision amplifiers dominate the power dissipation in most highspeed pipelined analogtodigital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple powerefficient openloop stages. In the multibit first stage of a 12bit 75MSamples/s proofofconcept prototype, we achieve more than 60 % residue amplifier power savings over a conventional implementation. The ADC has been fabricated in a 0.35 m doublepoly quadruplemetal CMOS technology and achieves typical differential and integral nonlinearity within 0.5 LSB and 0.9 LSB, respectively. At Nyquist input frequencies, the measured signaltonoise ratio is 67 dB and the total harmonic distortion is 74 dB. The IC consumes 290 mW at 3 V and occupies 7.9 mmP. Index Terms—Analogtodigital conversion, adaptive systems, calibration, CMOS analog integrated circuits, linearization techniques, parameter estimation. I.
An IC for linearizing RF power amplifiers using envelope elimination and restoration
 in ISSCC Digest of Technical Papers
, 1998
"... RF power amplifier linearization, envelope elimination and restoration, switching power supply, delta modulation, envelope detector, limiter, variable gain amplifier This paper presents a monolithic CMOS implementation of an envelope elimination and restoration linearization system that improves the ..."
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Cited by 11 (0 self)
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RF power amplifier linearization, envelope elimination and restoration, switching power supply, delta modulation, envelope detector, limiter, variable gain amplifier This paper presents a monolithic CMOS implementation of an envelope elimination and restoration linearization system that improves the linearity of efficient RF power amplifiers. The linearization IC, which occupies 4.3 mm 2 when implemented in a 0.8µm CMOS technology, consists of a limiter, envelope detectors, and a deltamodulated switching power supply. This circuit was used to linearize AMPS (Advanced Mobile Phone System) cellular power amplifiers transmitting NADC (North American Digital Cellular) waveforms. Measurements show that the linearized outputs meet the spectral mask and phase distortion requirements of NADC. The linearization system can improve the overall efficiency from 36 % to 49%, while increasing the maximum linear output power from 26.5dBm to 29.5dBm.
A 13bit, 1.4MS/s SigmaDelta Modulator for RF Baseband Channel Applications
 IEEE J. SolidState Circuits
, 1998
"... modulator oversampling at 16 X is implemented in a 0.72 "m complementary metal–oxide–semiconductor process for use in the baseband path of a radiofrequency receiver. The modulator achieves 77 dB of dynamic range and dissipates 81 mW from a 3.3 V supply. It is characterized for the blocking and ..."
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Cited by 10 (1 self)
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modulator oversampling at 16 X is implemented in a 0.72 "m complementary metal–oxide–semiconductor process for use in the baseband path of a radiofrequency receiver. The modulator achieves 77 dB of dynamic range and dissipates 81 mW from a 3.3 V supply. It is characterized for the blocking and intermodulation requirements of a cordless telephone application. Index Terms—Analog–digital conversion, radio receivers, sampleddata circuits, sigma–delta modulation, switchedcapacitor circuits. I.
A design methodology for highlyintegrated lowpower receivers for wireless communications
, 2001
"... ..."
A 14b 12MS/s CMOS Pipeline ADC With Over 100dB SFDR
 IEEE Journal of SolidState Circuits
, 2004
"... analogtodigital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gainboosting technique is described. The converter is optimized for lowvoltage lowpower applications by applying an optimum stagescaling algorithm at the architectural level and an opamp and co ..."
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Cited by 9 (1 self)
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analogtodigital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gainboosting technique is described. The converter is optimized for lowvoltage lowpower applications by applying an optimum stagescaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18 m 6M1P CMOS process, this converter achieves a peak signaltonoise plus distortion ratio (SNDR) of 75.5 dB and a 103dB spuriousfree dynamic range (SFDR) without trimming, calibration, or dithering. With a 1MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the frontend sampleandhold circuit is achieved using bootstrapped thinoxide transistors as switches, resulting in an SFDR of 97 dB when a 40MHz fullscale input is digitized. The ADC occupies an active area of 10 mmP and dissipates 98 mW. Index Terms—Analog integrated circuits, capacitor mismatch, comparator sharing, discretetime commonmode voltage regulation, early comparison, low power, low voltage, nested CMOS gain boosting, opamp sharing, passive capacitor erroraveraging, pipeline analogtodigital converter, pseudodifferential, subsampling. I.
A lowpower reconfigurable analogtodigital converter
 IEEE J. Solid State Circuits
, 2001
"... Abstract—A lowpower CMOS reconfigurable analogtodigital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta– ..."
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Cited by 7 (0 self)
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Abstract—A lowpower CMOS reconfigurable analogtodigital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta–sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phaselocked loop (PLL). This converter also incorporates several powerreducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta–sigma mode, and other design techniques. The opamp chopping technique achieves faster closedloop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0–10 MHz over a resolution range of 6–16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta–sigma mode, it achieves a maximum signaltonoise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of 0.55 LSBs and 0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with
HighSpeed AnalogtoDigital Converter Survey, unpublished
, 2005
"... Every year, higher and higher sampling rates as well as lower and lower power dissipations are reported in the literature. The table in Figure 1 lists published results for nineteen highspeed, lowresolution A/D converters (mostly six to eight bits), along with a few commercial parts, representing a ..."
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Cited by 4 (0 self)
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Every year, higher and higher sampling rates as well as lower and lower power dissipations are reported in the literature. The table in Figure 1 lists published results for nineteen highspeed, lowresolution A/D converters (mostly six to eight bits), along with a few commercial parts, representing a wide variety of fabrication technologies. In the following sections, these reported specifications are analyzed and compared. 1 Quantization Energy Figure of Merit The analog program committee of the IEEE International SolidState Circuits Conference suggested a figure of merit for A/D converters that takes into account power dissipation, resolution, and sampling rate [1]. It has units of energy, and represents the energy used per conversion step