The rapid development of Asynchronous Transfer Mode technology in the last 10-15 years has stimulated renewed interest in the design and analysis of switching systems, leading to new ideas for system designs and new insights into the performance and evaluation of such systems. As ATM moves closer to realizing the vision of ubiquitous broadband ISDN services, the design of switching systems takes on growing importance. This paper seeks to clarify the key architectural issues for ATM switching system design and provides a survey of the current state-of-the-art.

Improvements in fibre optic communication and in VLSI for network switching components have led to the consideration of building digital switched networks capable of providing point to point communication in the gigabit per second range. Provision of bandwidths of this magnitude allows the consideration of a whole new range of telecommunications services, integrating video, voice, image and text. These multi-service networks have a range of requirements not met by traditional network architectures designed for digital telephony or computer applications. This dissertation describes the design, and an implementation, of the Multi-Service Network architecture and protocol family, which is aimed at supporting these services. Asynchronous transfer mode networks provide the basic support required for these integrated services, and the Multi-Service Network architecture is designed primarily for these types of networks. The aim of the Multi-Service protocol family is to provide a complete arc...

One of the most promising approaches for high speed networks for integrated service applications is fast packet switching, or ATM (Asynchronous Transfer Mode). ATM can be characterized by very high speed transmission links and simple, hardwired protocols within a network. To match the transmission speed of the network links, and to minimize the overhead due to the processing of network protocols, the switching of cells is done in hardware switching fabrics in ATM networks. A number of designs have been proposed for implementing ATM switches. While many differences exist among the proposals, the vast majority of them is based on self-routing multi-stage interconnection networks. This is because of the desirable features of multi-stage interconnection networks such as self--routing capability and suitability for VLSI implementation. Existing ATM switch architectures can be classified into two major classes: blocking switches, where blockings of cells may occur within a switch when more t...

As the communications industry continues to expand two current trends are becoming apparent: the desire to support an increasing diversity of communications services #voice, video, image, text, etc.# and the consequent requirement for increased network capacity to handle the expected growth in suchmulti-service tra#c. This dissertation describes the design, performance and implementation of a high capacity switch which uses fast packet switching to o#er the integrated support of multi-service tra#c. Applications for this switch are considered within the public network, in the emerging metropolitan area network and within local area networks. The Cambridge Fast Packet Switch is based upon a non-bu#ered, multi-path switch fabric with packet bu#ers situated at the input ports of the switch. This results in a very simple implementation suitable for construction in current gate array technology. A simulation study of the throughput at saturation of the switch is #rst presented to select th...

Asynchronous transfer mode (ATM) and fast packet switching offer the ability to support many diverse forms of telecommunications services across a single integrated network. Some applications require the communications traffic from a single source to be received concurrently by many destinations. One approach to satisfy this requirement is to use a copy fabric to replicate the necessary number of copies of the incident traffic and then to route each copy to the required destination in a conventional point-to-point ATM fast packet switch. This paper presents the design and performance of a copy fabric based upon a slotted ring that permits a very simple implementation. It offers a performance which for many applications is comparable to that of much more complex designs.

Abstract|In this paper, a new switcharchitecture with quasi-shared bu ering is proposed for a scalable multicast ATM switch system. The proposed switch shares a small size of dedicated bu ers for its input and output ports, and incoming cells are e ectively distributed within the switch system. For sharing dedicated bu ers, a distributor is proposed to evenly distribute incoming cells into dedicated bu ers and an arbiter is also proposed to resolve the contentions of cells destined for the same output port. Since parallel processing techniques are applied to implementing the distributor and arbiter, the structure is simple and thus the processing is fast. Other features of the proposed switch architecture include scalability, no degradation in throughput with increasing the multicast cell ratio, and expandability to asymmetric switches. Finally, the performance of the proposed switch architecture is evaluated through simulations in terms of throughput, mean delay, cell loss probability, and cell sequence error probability. I.

When planning the future telecommunications network, it will be crucial to know what ATM switch fabrics exist, and what their relative merits are for different applications. This report is intended as the first step towards obtaining such information. All current ATM switch fabrics are categorised, comments being made regarding their performance, control, fault tolerance, complexity, growability, scalability and feasibility. Recommendations are made for further work in this area, on categorisations and review, and on cost/performance evaluation. Contents 1 Executive Summary 3 2 Introduction 6 3 ATM Cross-Connects and Exchanges 6 4 Criteria for Comparison of Switch Elements 8 5 Classi#cation Tree 11 6 Input Bu#ering 11 6.1 The Three Phase Switch #Bellcore, 1987# :::::::::::::::::: 13 6.2 The NEMAWASHI Switch #OKI, 1990#* ::::::::::::::::::: 14 6.3 A Three Phase Switch with 2-Replicated Banyan Networks #Universityof Bologna, 1989# ::::::::::::::::::::::::::::::::: 16 6.4 The TSC...