Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point in the buses to study the severity of the voltage drop problems and to redesign the supply lines accordingly. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this paper, we propose a patternindependent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit. The algorithm is extremely efficient an...

This paper deals with the problem of estimating the average power consumption (per clock cycle) of CMOS digital circuits. A new pattern-independent method is proposed for computing an upper bound on the switching activity, and therefore the average power, of a combinational circuit described at the gate level. The method is based on the propagation of abstract waveform sets, described down to the level of individual transitions. The view of a gate as a relation between input and output signals, described by forward and partial inverse functions, permits the determination of a tight upper bound on the power using a constraint resolution method based on waveform narrowing. A fully scalable, case analysis-based algorithm provides at any step an upper bound and, with enough resources (CPU time), it can continue up to the exact solution. The paper presents the theoretical background, a description of the implementation, and results on benchmark circuits. 1. Introduction Both the scaling o...