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A 1.9GHz wideband IF double conversion CMOS receiver for cordless telephone applications
 IEEE Journal of SolidState Circuits
, 1997
"... Rapid growth in the portable communications market has pushed designers to seek lowcost, lowpower, highly integrated solutions for the RF transceiver. A number of recent efforts have concentrated on integrating many of the discrete radio receiver components in a lowcost silicon process such as CM ..."
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Rapid growth in the portable communications market has pushed designers to seek lowcost, lowpower, highly integrated solutions for the RF transceiver. A number of recent efforts have concentrated on integrating many of the discrete radio receiver components in a lowcost silicon process such as CMOS [1][2]. This paper describes a prototype of a monolithic CMOS receiver that combines RF and baseband functionality by taking the carrier signal at the LNA input and producing a 10bit digital baseband waveform. A WideBand Intermediate Frequency Double Conversion (WBIFDC) architecture is utilized to remove the need for external narrowband IF filters.
An analog VLSI chip for estimating the focus of expansion
 In 1997 ISSCC Digest of Technical Papers
, 1996
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A Parallel Structure for CMOS FourQuadrant Analog Multipliers and its Application to a 2 GHz RF Downconversion Mixer
 IEEE J. SolidState Circuits
, 1998
"... Abstract—A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog ..."
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Cited by 6 (0 self)
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Abstract—A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog multiplier is designed and fabricated by 0.8m Nwell doublepolydoublemetal CMOS technology. Experimental results have shown that, under a single 1.2V supply voltage, the circuit has 0.89 % linearity error and 1.1 % total harmonic distortion under the maximumscale input 500mV PP at both multiplier inputs. The 3dB bandwidth is 2.2 MHz and the dc current is 2.3 mA. By using the proposed multiplier as a mixercore and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5m singlepolydoublemetal Nwell CMOS technology. The experimental results have shown that, under 3V supply voltage and 2dBm LO power, the mixer has 1dB conversion gain, 2.2GHz input bandwidth, 180MHz output bandwidth, and 22dB noise figure. Under the LO frequency 1.9 GHz and the total dc current 21 mA, the thirdorder input intercept point is +7.5 dBm and the input 1dB compression point is 9 dBm. Index Terms—Analog multiplier, low voltage, RF mixer, wireless communication. I.
A lowpower CMOS analog multiplier
 IEEE Trans. Circuits Syst., II, Exp. Briefs
, 2006
"... Abstract—A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design considerations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low po ..."
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Abstract—A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design considerations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low power consumption with comparable linearity and noise performance, making it very attractive for use in a variety of analog circuits. Index Terms—Analog integrated circuits, analog multipliers, CMOS, lowpower design. I.
Hippocampal Formation v TABLE OF CONTENTS
, 1993
"... Iwould especially like to thank Steve Levitan and Robert Sclabassi for their guidance, support and patience throughout the development of this project; Steve Frezza and YeeWing Hsieh for reading my thesis and correcting the grammatical mistakes. Finally, special thanks to my parents, Kwan Yeung Chi ..."
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Iwould especially like to thank Steve Levitan and Robert Sclabassi for their guidance, support and patience throughout the development of this project; Steve Frezza and YeeWing Hsieh for reading my thesis and correcting the grammatical mistakes. Finally, special thanks to my parents, Kwan Yeung Chiu and Kwan Chan Yin Fong; my sisters, Grace, Claudine and Josephine, for their support.
doi:10.3906/elk1001377
"... A novel fourquadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement t ..."
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A novel fourquadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only six FGMOS transistors. The main features of this remarkably simple multiplier circuit configuration are the large input signal range equal to 100 % of the supply voltage, nonlinearity of 0.0081%, bandwidth of 1.4–1.5 Ghz and THD of maximum 2.67 % (while the inputs are at their maximum values). Key Words: FGMOS, four quadrant analog multiplier, railtorail, differential amplifier 1.