Recent efforts in the design of wireless RF transceivers focus on high integration and multi-standard operation. Higher integration can be obtained by using receiver architectures, such as wide-band IF with double conversion (WIF), that perform channel select filtering on-chip at baseband. Performing this baseband channel select filtering in the digital domain allows for the programmability necessary to adapt to the different channel bandwidths, sampling rates, and CNR requirements of multiple communication standards. At the back of a wide-dynamic range sigma-delta modulator, a decimation filter can select a desired channel in the presence of both strong adjacent channel interferers and quantization noise from the digitization process. A low-power decimation filter that performs channel select filtering for the GSM (European cellular) and DECT (European cordless) standards is presented. Automatic gain control is used within the filter to reduce the dynamic range and power consumption. Since the two standards have different blocking profiles and CNR i

This paper presents a study of LO selfmixing and RF gain control issues in direct conversion receivers. In cellular systems, that use continuous time frequency duplexing, these can constitute serious problems. The presented topic is of special importance when digitally programmable gain is implemented at the RF frequencies before the downconversion mixers, practically in the LNA. Furthermore, this paper gives circuit solutions to overcome this problem. 1.

A major focus of recent RF transceiver IC designs has been to increase both the integration and adaptability to multiple RF communication standards. Performing channel selection on chip at baseband allows the use of high-integration receiver architectures, and enhances programmability to different channel bandwidths and dynamic range requirements of multiple RF standards. A wideband, high-dynamic range sigma-delta modulator can be used to digitize both the desired signal and potentially stronger adjacent-channel interferers. In the digital domain, the decimation filter following the ADC can be easily made programmable. A 4th-order sigma-delta ADC which is capable of adapting to GSM (cellular) and DECT (cordless) communication standards is described. The ADC achieves 14 bits of resolution at 128x oversampling ratio (200kS/s Nyquist rate) for GSM, and 12 bits of i resolution at 32x oversampling ratio (1.4MS/s Nyquist rate) for DECT. Power reduction strategies are developed at both the sigma-delta architecture and circuit design levels. The experimental prototype, fabricated in a 0.35μm CMOS process, dissipates 70mW from a 3.3V supply.

High-Speed, Low-Power Sigma-Delta Modulators for RF Baseband Channel Applications by Arnold R. Feldman Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences University of California, Berkeley Professor Paul R. Gray, Chair Abstract 2 the new architecture and verify the effectiveness of the power reduction strategies. The modulator achieves 71 dB of peak SNDR and 77 dB of dynamic range. The chip dissipates 81 mW from a 3.3 V supply at 1.4 MS/s Nyquist rate and 16 X oversampling ratio. Paul R. Gray, Chairman of Committee Acknowledgments iii Acknowledgments First, I would like to acknowledge my advisor, Professor Paul Gray, for his guidance and support during my stay at Berkeley. His insight into circuit design and ability to keep me focussed on the big picture was critical to the project's success. I also want to thank Professor Bernhard Boser for his invaluable help and especially for sharing his sigma-delta architecture and circuit design expertise. ...

Since several years the research in the possibilities of CMOS technologies for RF applications is growning enormously. The trend towards deep sub-micron technologies allows the operation frequency of CMOS circuits above 1GHz, which opens the way to integrated CMOS RF circuits. Several research groups have developed high performance down-converters, low phase noise voltage controlled oscillators and dual modulus prescalers in standard CMOS technologies. The research has already demonstrated fully integrated receivers and VCO circuits with no external components, nor tuning or trimming. Further research on low noise amplifiers, up-converters, synthesizers and power amplifiers will hopefully result in CMOS RF circuits for fully integrated transceivers for telecommunication applications. 1. Introduction A few years ago the world of wireless communications and its applications started to grow rapidly. The driving force for this is the introduction of digital coding and digital s...

Abstract—This paper describes the design and implementation of a 2-GHz single-chip 0.25-µm CMOS receiver for a custom WCDMA system. A system-level simulation framework is used to explore the trade-offs between analog front-end impairments and system performance. System specifications are chosen in order to facilitate a low-power highly-integrated implementation. The receiver is based on a direct-conversion architecture and implements all RF components, including the low-noise amplifier, frequency synthesizer, and mixers. The receiver also integrates all baseband components along the in-phase and quadrature signal paths, each of which includes a first-order high-pass filter, a second-order Sallen and Key low-pass filter, and a 7-bit, 25-MS/s Σ ∆ analog-to-digital converter operating at 200 MHz. The receiver prototype achieves an 8.5-dB noise figure, provides 41-dB voltage gain, and dissipates 106 mW. I.