. This paper describes an ongoing effort to verify the cache coherence protocol of the IEEE/ANSI Standard for Scalable Coherent Interface using the Mur' verification system. A model of the typical set protocol was constructed in the Mur' description language. This model was augmented with a specification of properties necessary for cache coherence. The Mur' verification system automatically checks if all reachable states in the model satisfy the given specification. Although verification is still under way, we have already found several errors in the C-code defining the protocol. Finally, we elucidate the experiences gained in the verification project. 1 Introduction The IEEE/ANSI Standard for Scalable Coherent Interface (SCI) includes a cache coherence protocol for distributed shared-memory multiprocessors. Designing a complex protocol -- like this cache coherence protocol -- is a challenging and difficult task. It is very hard for a designer to predict all possible interactions amon...

There is rapidly increasing demand for very high performance shared access to distributed data, for multiprocessors, networked workstation clusters, distributed databases, industrial data acquisition and control systems, etc. The objective is to satisfy this demand at the lowest longterm cost. This paper first considers the general properties that an appropriate system architecture should have. A new architectural model, Local-Area MultiProcessor, is introduced. These properties are then considered in more detail, and practical design decisions are made, illustrated by the evolution of the ISO/ANSI/IEEE standard Scalable Coherent Interface (SCI) as it addressed these issues. Finally, the current status of the various SCI follow-on and support projects is reported.

Modern digital systems often employ sophisticated protocols. Unfortunately, designing correct protocols is a subtle art. Even when using great care, a designer typically cannot foresee all possible interactions among the components of the system; thus, bugs like subtle race conditions or deadlocks are easily overlooked. One way a computer can support the designer is by simulating random executions of the system. There is, however, a high probability of missing executions containing errors -- especially in complex systems -- using this simulation approach. In contrast, an automatic verifier tries to examine all states reachable from a given set of startstates. The biggest obstacle in this exhaustive approach is that often there is a very large number of reachable states. This thesis describes three techniques to increase the size of the reachable state spaces that can be handled in automatic verifiers. The techniques work in verifiers that are based on explicitly storing each reachable ...

Practical parallel machines which are parallel virtual machine (PVP), symmetric multiprocessor (SMP), massively parallel processor (MPP), distributed shared memory (DSM), and clusters of workstation (COWs) are described. According to the classification of practical parallel machines, this paper mainly deals with distributed shared memory (DSM). The concept of DSM is explained, and the comparison among software, hardware, and hybrid DSM implementations are presented.

Clusters of Symmetrical Multiprocessor machines are increasingly becoming the norm for high performance computing environments. The Automatic Parallelization Environment (APE) has recently been proposed as a new environment for solving large scale scientific and engineering problems on such computing platforms. This work extends current research in parallelizing compilers and runtime environments to convert existing sequential programs for execution on such clusters of Symmetrical Multiprocessors (SMPs). The first phase of this work addresses the selection of the front-end compiler for APE. The SUIF compiler is selected for integration into the system and its performance is evaluated with some benchmark codes, and Computational Fluid Dynamics kernels. The compiler is shown to provide close to linear speedups for some of the kernel code. The compiler currently produces code for a single shared-memory multiprocessor system. The use of a software Distributed Shared Memory (DSM) system is hence suggested in order to provide a portable target for the compiler. An evaluation of existing DSMs, SAM, CRL and Quarks shows that they cannot be directly used within the existing framework. A new, multithreaded DSM system, Strings is proposed and its performance compared to other existing systems using programs from the SPLASH-2 benchmark suite, some computational kernels and a full application. The last part focuses on integrating the compiler with the DSM. An additional pass called suif2strings is added to the parallelizing SUIF compiler. The overhead added due to this pass is evaluated with the NAS serial benchmarks, and results with some computational kernels are shown. The complete work thus serves as an initial implementation and testbench for the APE.