Abstract. We revisit monotone planar circuits MPCVP, with special attention to circuits with cylindrical embeddings. MPCVP is known to be in NC 3 in general, and in LogDCFL for the special case of upward stratified circuits. We characterize cylindricality, which is stronger than planarity but strictly generalizes upward planarity, and make the characterization partially constructive. We use this construction, and four key reduction lemmas, to obtain several improvements. We show that monotone circuits with embeddings that are stratified cylindrical, cylindrical, planar one-input-face and focused can be evaluated in LogDCFL, AC 1 (LogDCFL), LogCFL and AC 1 (LogDCFL) respectively. We note that the NC 3 algorithm for general MPCVP is in AC 1 (LogCFL) =SAC 2.Finally, we show that monotone circuits with toroidal embeddings can, given such an embedding, be evaluated in NC. 1

We consider the computational power of constant width polynomial size cylindrical circuits and nondeterministic branching programs. We show that every function computed by a #2 circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching program (or cylindrical circuit) and that every function computed by a constant width polynomial size cylindrical circuit belongs to ACC .

We show that ACC is precisely what can be computed with constant-width circuits of polynomial size and polylogarithmic genus. This extends a characterization given by Hansen, showing that planar constant-width circuits also characterize ACC. Thus polylogarithmic genus provides no additional computational power in this model. We consider other generalizations of planarity, including crossing number and thickness. We show that thickness two already suffices to capture all of NC. 1

and for the special case of upward stratified circuits, it is known to be in LogDCFL. In this paper we re-examine the complexity of MPCVP, with special attention to circuits with cylindrical embeddings. We characterize cylindricality, which is stronger than planarity but strictly generalizes upward planarity, and make the characterization partially constructive. We use this construction, and four key reduction lemmas, to obtain several improvements. We show that stratified cylindrical monotone circuits can be evaluated in LogDCFL, and arbitrary cylindrical monotone circuits can be evaluated in AC 1 (LogDCFL), while monotone circuits with one-input-face planar embeddings can be evaluated in LogCFL. For monotone circuits with focused embeddings, we show an upper bound of AC 1 (LogDCFL). We re-examine the NC 3 algorithm for general MPCVP, and note that it is in AC 1 (LogCFL) = SAC 2. Finally, we consider extensions beyond MPCVP. We show that monotone circuits with toroidal embeddings can, given such an embedding, be evaluated in NC. Also, special kinds of arbitrary genus circuits can also be evaluated in NC. We also show that planar non-monotone circuits with polylogarithmic negation-height can be evaluated in NC.

In this thesis, we deal largely with complexity theoretic aspects in planar restrictions and obliviousness. Our main motivation was to identify problems for which the planar restriction is much easier, computationally, than the unrestricted version. First, we study constant width polynomial-sized circuits of low (polylogarithmic) genus; we show how such circuits characterize exactly the well-known circuit complexity class ACC0 (given that the unrestricted version captures the whole of NC1). We also give a new circuit characterization of the class NC1. Shifting our focus from circuits to graphs, we look at different notions of connectivity. We investigate the directed planar graph reachability problem, as a possibly more tractable special case of the arbitrary graph reachability problem (which is NL-complete). We prove that this problem logspace-reduces to its complement, and also that reachability questions on genus 1 graphs reduce to that in planar graphs. We also prove that reachability in a particularly simple class of planar graphs (namely, grid graphs) is no easier than the general directed planar reachability question. We then proceed to isolate to several large classes of planar graphs for which the reachability questions are solvable in deterministic logspace. Counting the number of spanning trees in a graph is a useful extension of the task of determining

Abstract. Spira [28] showed that any Boolean formula of size s can be simulated in depth O(log s). We generalize Spira’s theorem and show that any Boolean circuit of size s with segregators of size f(s) can be simulated in depth O(f(s) log s). If the segregator size is at least s ε for some constant ε> 0, then we can obtain a simulation of depth O(f(s)). This improves and generalizes a simulation of polynomial-size Boolean circuits of constant treewidth k in depth O(k 2 log n) by Jansen and Sarma [17]. Since the existence of small balanced separators in a directed acyclic graph implies that the graph also has small segregators, our results also apply to circuits with small separators. Our results imply that the class of languages computed by non-uniform families of polynomial-size circuits that have constant size segregators equals non-uniform NC 1. Considering space bounded Turing machines to generate the circuits, for f(s) log 2 s-space uniform families of Boolean circuits our small-depth simulations are also f(s) log 2 s-space uniform. As a corollary, we show that the Boolean Circuit Value problem for circuits with constant size segregators (or separators) is in deterministic SP ACE(log 2 n). Our results also imply that the Planar Circuit Value problem, which is known to be P-Complete [16], can be solved in deterministic SP ACE ( √ n log n). Key words: Boolean circuits, circuit size, circuit depth, Spira’s theorem, Turing machines, space complexity 1