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Evaluating monotone circuits on cylinders, planes, and tori
 IN PROC. 23RD SYMPOSIUM ON THEORETICAL ASPECTS OF COMPUTING (STACS), LECTURE NOTES IN COMPUTER SCIENCE
, 2006
"... We revisit monotone planar circuits MPCVP, with special attention to circuits with cylindrical embeddings. MPCVP is known to be in NC 3 in general, and in LogDCFL for the special case of upward stratified circuits. We characterize cylindricality, which is stronger than planarity but strictly gener ..."
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We revisit monotone planar circuits MPCVP, with special attention to circuits with cylindrical embeddings. MPCVP is known to be in NC 3 in general, and in LogDCFL for the special case of upward stratified circuits. We characterize cylindricality, which is stronger than planarity but strictly generalizes upward planarity, and make the characterization partially constructive. We use this construction, and four key reduction lemmas, to obtain several improvements. We show that monotone circuits with embeddings that are stratified cylindrical, cylindrical, planar oneinputface and focused can be evaluated in LogDCFL, AC 1 (LogDCFL), LogCFL and AC 1 (LogDCFL) respectively. We note that the NC 3 algorithm for general MPCVP is in AC 1 (LogCFL) =SAC 2.Finally, we show that monotone circuits with toroidal embeddings can, given such an embedding, be evaluated in NC.
Circuits on Cylinders
, 2002
"... We consider the computational power of constant width polynomial size cylindrical circuits and nondeterministic branching programs. We show that every function computed by a #2 circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching program (o ..."
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Cited by 9 (3 self)
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We consider the computational power of constant width polynomial size cylindrical circuits and nondeterministic branching programs. We show that every function computed by a #2 circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching program (or cylindrical circuit) and that every function computed by a constant width polynomial size cylindrical circuit belongs to ACC .
LTL path checking is efficiently parallelizable
 Proc. 36th Int. Conf. Autom. Lang. Program., Part II, Rhodes (Susanne Albers, Alberto MarchettiSpaccamela, Yossi Matias, Sotiris E. Nikoletseas and Wolfgang Thomas, eds.), LNCS 5556, 235– 246, 2009. Leslie Lamport. ‘Sometime’ is sometimes ‘not never’, Pr
"... Abstract. We present an AC 1 (logDCFL) algorithm for checking LTL formulas over finite paths, thus establishing that the problem can be efficiently parallelized. Our construction provides a foundation for the parallelization of various applications in monitoring, testing, and verification. Linearti ..."
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Abstract. We present an AC 1 (logDCFL) algorithm for checking LTL formulas over finite paths, thus establishing that the problem can be efficiently parallelized. Our construction provides a foundation for the parallelization of various applications in monitoring, testing, and verification. Lineartime temporal logic (LTL) is the standard specification language to describe properties of reactive computation paths. The problem of checking whether a given finite path satisfies an LTL formula plays a key role in monitoring and runtime verification [12,10,6,1,4], where individual paths are checked either online, during the execution of the system, or offline, for example based on an error report. Similarly, path checking occurs in testing [2] and in several static verification techniques, notably in MonteCarlobased probabilistic verification, where large numbers of randomly generated sample paths are analyzed [22]. Somewhat surprisingly, given the widespread use of LTL, the complexity of the path checking problem is still open [18]. The established upper bound is P: The algorithms in the literature traverse the path sequentially (cf. [10,18,12]);
A Generalization of Spira’s Theorem and Circuits with Small Segregators or Separators
"... Abstract. Spira [28] showed that any Boolean formula of size s can be simulated in depth O(log s). We generalize Spira’s theorem and show that any Boolean circuit of size s with segregators of size f(s) can be simulated in depth O(f(s) log s). If the segregator size is at least s ε for some constant ..."
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Abstract. Spira [28] showed that any Boolean formula of size s can be simulated in depth O(log s). We generalize Spira’s theorem and show that any Boolean circuit of size s with segregators of size f(s) can be simulated in depth O(f(s) log s). If the segregator size is at least s ε for some constant ε> 0, then we can obtain a simulation of depth O(f(s)). This improves and generalizes a simulation of polynomialsize Boolean circuits of constant treewidth k in depth O(k 2 log n) by Jansen and Sarma [17]. Since the existence of small balanced separators in a directed acyclic graph implies that the graph also has small segregators, our results also apply to circuits with small separators. Our results imply that the class of languages computed by nonuniform families of polynomialsize circuits that have constant size segregators equals nonuniform NC 1. Considering space bounded Turing machines to generate the circuits, for f(s) log 2 sspace uniform families of Boolean circuits our smalldepth simulations are also f(s) log 2 sspace uniform. As a corollary, we show that the Boolean Circuit Value problem for circuits with constant size segregators (or separators) is in deterministic SP ACE(log 2 n). Our results also imply that the Planar Circuit Value problem, which is known to be PComplete [16], can be solved in deterministic SP ACE ( √ n log n). Key words: Boolean circuits, circuit size, circuit depth, Spira’s theorem, Turing machines, space complexity 1
Topology inside NC¹
"... We show that ACC⁰ is precisely what can be computed with constantwidth circuits of polynomial size and polylogarithmic genus. This extends a characterization given by Hansen, showing that planar constantwidth circuits also characterize ACC⁰. Thus polylogarithmic genus provides no additional comput ..."
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Cited by 1 (1 self)
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We show that ACC⁰ is precisely what can be computed with constantwidth circuits of polynomial size and polylogarithmic genus. This extends a characterization given by Hansen, showing that planar constantwidth circuits also characterize ACC⁰. Thus polylogarithmic genus provides no additional computational power in this model. We consider other generalizations of planarity, including crossing number and thickness. We show that thickness two already suffices to capture all of NC¹.
COMPLEXITY THEORETIC ASPECTS OF PLANAR RESTRICTIONS AND OBLIVIOUSNESS
, 2006
"... In this thesis, we deal largely with complexity theoretic aspects in planar restrictions and obliviousness. Our main motivation was to identify problems for which the planar restriction is much easier, computationally, than the unrestricted version. First, we study constant width polynomialsized ci ..."
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In this thesis, we deal largely with complexity theoretic aspects in planar restrictions and obliviousness. Our main motivation was to identify problems for which the planar restriction is much easier, computationally, than the unrestricted version. First, we study constant width polynomialsized circuits of low (polylogarithmic) genus; we show how such circuits characterize exactly the wellknown circuit complexity class ACC0 (given that the unrestricted version captures the whole of NC1). We also give a new circuit characterization of the class NC1. Shifting our focus from circuits to graphs, we look at different notions of connectivity. We investigate the directed planar graph reachability problem, as a possibly more tractable special case of the arbitrary graph reachability problem (which is NLcomplete). We prove that this problem logspacereduces to its complement, and also that reachability questions on genus 1 graphs reduce to that in planar graphs. We also prove that reachability in a particularly simple class of planar graphs (namely, grid graphs) is no easier than the general directed planar reachability question. We then proceed to isolate to several large classes of planar graphs for which the reachability questions are solvable in deterministic logspace. Counting the number of spanning trees in a graph is a useful extension of the task of determining
This document in subdirectoryRS/02/50/ Circuits on Cylinders
, 2002
"... Reproduction of all or part of this work is permitted for educational or research use on condition that this copyright notice is included in any copy. See back inner page for a list of recent BRICS Report Series publications. Copies may be obtained by contacting: BRICS ..."
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Reproduction of all or part of this work is permitted for educational or research use on condition that this copyright notice is included in any copy. See back inner page for a list of recent BRICS Report Series publications. Copies may be obtained by contacting: BRICS
PARALLEL COMPLEXITY CLASSES CENTERED AROUND LOGCFL By
, 2005
"... Certified that this dissertation titled Parallel Complexity Classes Centered Around LogCFL is the bonafide work of Miss. Nutan Limaye who carried out the project under my supervision. Certified further, that to the best of my knowledge the work reported herein does not form part of any other dissert ..."
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Certified that this dissertation titled Parallel Complexity Classes Centered Around LogCFL is the bonafide work of Miss. Nutan Limaye who carried out the project under my supervision. Certified further, that to the best of my knowledge the work reported herein does not form part of any other dissertation of the basis of which a degree or award was conferred on an earlier occasion for this or any other candidate.
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"... We show that ACC 0 is precisely what can be computed with constantwidth circuits of polynomial size and polylogarithmic genus. This extends a characterization given by Hansen, showing that planar constantwidth circuits also characterize ACC 0. Thus polylogarithmic genus provides no additional comp ..."
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We show that ACC 0 is precisely what can be computed with constantwidth circuits of polynomial size and polylogarithmic genus. This extends a characterization given by Hansen, showing that planar constantwidth circuits also characterize ACC 0. Thus polylogarithmic genus provides no additional computational power in this model. We consider other generalizations of planarity, including crossing number and thickness. We show that thickness two already suffices to capture all of NC 1. 1