Abstract. The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a v ¯ ariable input delay(VID) gate and the maximum difference in delay between any two paths through the same gate is known as “ub”. These gates can be used for minimizing the active power of a digital CMOS circuit using a previosuly described technique called v ¯ ariable input delay(VID) logic. This previous publication proposed three different designs for implementating the VID gate. In this paper, we describe a technique for transistor sizing of these three flavors of the VID gate for a given delay requirement. We also describe techniques for calculating the ub of each flavor. We outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance. 1

A gate that offers different delays for different input-output paths through it, is known as a variable input delay (VID) gate. The upper bound on this differential delay capability is specified by the parameter “ub”. These gates can be used to minimize the active power of a digital CMOS circuit by a path balancing and glitch filtering techniques discussed in recent publications. In this paper, we describe transistor sizing methods for three types of VID gates that satisfy given delay requirements. The three ways to obtain the differential delays are capacitance manipulation, nMOS transistor insertion, and CMOS transmission gate insertion. We also describe techniques for calculating the ub of each VID gate type. Finally, we outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance. 1

The single biggest influence on this work is Nur Touba, who got me started in the field of design automation for VLSI. Nur's unflagging support and encouragement have sustained and driven me throughout the last five years. To the extent that the work presented herein is worthy of credit, Nur deserves a large portion of that credit. His standards in professionalism, integrity, and honesty have raised the bar of excellence for me to follow. Another important influence is Gustavo De Veciana, whose professional life is grounded in a deep understanding of and love for electrical engineering and the teaching and learning process. Words cannot do justice to express all that Gustavo's mentoring has come to mean to me. Thanks also to Margarida Jacome, not just for her support on my dissertation committee, but also for her encouragement and particularly forceful endorsement that has helped me embark on a career in academics. I must also thank Dinos Moundanos and Jawahar Jain for their part in making my stay at and collaborations with the Fujitsu Laboratories of America highly productive. It was there that I took my first tentative steps into the world of research and there that I found the courage and confidence to pursue my own ideas. I would also like to

Abstract---It is known that input reordering of a gate affects the power dissipated by the internal capacitance of the reordered gate, which has been utilized for power reduction so far. We show that the reordering also has a significant effect on the power dissipation of the gate which drives the reordered gate. It is because the input capacitance depends on signal values of other inputs. We propose a reordering algorithm considering the power dissipation in the driving gate, the reordered gate and the gates driven by the reordered gate. Experimental results using 21 benchmark circuits show that our method reduces the power dissipation in all the circuits by 3.6 % on average. There is a possibility that power dissipation is reduced by 17.2 % maximum. In the case of delay and power optimization, our method reduces delay by 7.0 % and power dissipation by 3.1 % on average. I.