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Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint
 Proc. of Int'l Symp. on Low Power Design, Monterey CA
, 1995
"... We consider the problem of transistor sizing in a static CMOS layout to minimize the power consumption of the circuit subject to a given delay constraint. Based on our characterization of the short circuit power dissipation of a CMOS circuit we show that the transistors of a gate with high fanout l ..."
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We consider the problem of transistor sizing in a static CMOS layout to minimize the power consumption of the circuit subject to a given delay constraint. Based on our characterization of the short circuit power dissipation of a CMOS circuit we show that the transistors of a gate with high fanout load should be enlarged to minimize the power consumption of the circuit. We derive analytical formulation for computing the power optimal size of a transistor and isolate the factor a ecting the power optimal size. We extend our model to analyze powerdelay characteristic of a CMOS circuit and derive the powerdelay optimal size of a transistor. Based on our model we develop heuristics to perform transistor sizing in CMOS layouts for minimizing power consumption while meeting given delay constraints. Experimental results (SPICE simulations) are presented to con rm the correctness of our analytical model. 1
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
 in Proc. of 16th International Conference on VLSI Design
, 2003
"... In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay,we ..."
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Cited by 20 (10 self)
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In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay,we reduce the number of the LP constraints to be linear in circuit size. For example, the 469gate c880 circuit requires 3,611 constraints as compared to the 6.95 million constraints needed with the previous method. The reduced constraints provably produce the same exact LP solution as obtained by the exponential set of constraints. For the rst time, we are able to optimize all ISCAS'85 benchmarks. For the c7552 circuit, when the input to output delay is constrained not to increase, a design with 366 delay bu ers consumes only 34 % peak and 38 % average power as compared to an unoptimized design. As shown in previous work, the use of delay bu ers is essential in this case. The practicality of the design is demonstrated by implementing an optimized 4bit ALU circuit for which the power consumption was obtained by a circuitlevel simulator. 1.
Optimizing CMOS Circuits for Low Power using Transistor Reordering
, 1995
"... This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power of internal nodes of the gate. This powerconsumption model depends on the switching activity and the eq ..."
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This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power of internal nodes of the gate. This powerconsumption model depends on the switching activity and the equilibrium probabilities of the inputs of the gate. The model allows an exploration of the different configurations of a gate that are obtained by reordering its transistors. Thus, the best configuration of each gate is selected and the overall power consumption of the circuit is reduced. 1 Introduction The continuous increasing packing density and clock frequency of static CMOS circuits has pushed low power as one of the principal design parameters, specially in batterypowered portable systems, such as notepad computers, personal digital assistants, multimedia terminals and mobile telephones. This paper addresses the optimization of a circuit for low power using transistor reordering fr...
LowPower Multimedia DSP Systems
 Proc. of 1997 Int. Conf. on VLSI and CAD (ICVC), Seoul, Korea
, 1997
"... In a few years, multimedia will become part of everyone's life. This paper presents an overview of DSP processors which are targeted for multimedia applications. Current and future trends of these processors are predicted. Reduction of power consumption in these systems is one of the major chal ..."
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In a few years, multimedia will become part of everyone's life. This paper presents an overview of DSP processors which are targeted for multimedia applications. Current and future trends of these processors are predicted. Reduction of power consumption in these systems is one of the major challenges for implementation. Various techniques for reduction of power consumption are reviewed. 1. Introduction The last decade has seen tremendous growth in the field of communication and computing. Much of this growth has been fueled by the promise of multimedia  an exciting array of new products and services, ranging from video games, car navigators, web surfing, to interactive television, cellular and video phones, personal digital assistants, video on demand, and desktop video conferencing. In addition to conventional user interfaces and I/O operations, these multimedia applications demand realtime digital signal processing (DSP) to support compression and decompression of audio, speech, ...
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"... Abstract: This paper presents analytical derivation of optimum width of CMOS transistors to minimize losses in monolithic buck converters. High optimal width of CMOS transistors entails use of tapered inverter chain as gate driver. A novel technique called “widthswitching ” is presented, which can ..."
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Abstract: This paper presents analytical derivation of optimum width of CMOS transistors to minimize losses in monolithic buck converters. High optimal width of CMOS transistors entails use of tapered inverter chain as gate driver. A novel technique called “widthswitching ” is presented, which can be easily incorporated along with the inverter chain to maintain maximum efficiency of buck converter over a range of output power levels. Experimental results from a chip containing optimal CMOS transistors for power levels between 50 mW and 200 mW are presented. Challenges in implementing the widthswitching scheme, and technologies in which similar schemes can be used, are also discussed. I.
A Generalized Minimum Dynamic Power and HighSpeed Design Methods for . . .
, 2004
"... We formulate a linear program (LP) to simultaneously minimize the dynamic power and overall delay of a CMOS circuit. To eliminate all glitches either without or with minimal number of delay buffers, a CMOS gate is assumed to have adjustable input to output delays for each input. Since these delays a ..."
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We formulate a linear program (LP) to simultaneously minimize the dynamic power and overall delay of a CMOS circuit. To eliminate all glitches either without or with minimal number of delay buffers, a CMOS gate is assumed to have adjustable input to output delays for each input. Since these delays are not independent, a transistor sizing problem would require very complex nonlinear optimization. We solve the problem in three steps. First, CMOS gates are analyzed to determine the realizable maximum differential input delay, ub, for the device technology being used. Second, an LP assumes the gate input and output delays as independent variables and determines them for all gates. This LP satisfies (1) glitch elimination conditions and the realizability constraint (ub) for all gates, and (2) the specified overall delay for the circuit. The total number of constraints in our LP is a linear function of the circuit size. Third, all gates are designed with the delays determined by the LP. As a sample result, using ub =10 when we designed the c1355 benchmark circuit specifying a large overall delay, a zero buffer design was obtained. It consumed 33 % power and had three times the overall delay as compared to an unoptimized design. When the overall delay was constrained not to increase, the lowpower design required 64 delay bu ers and consumed 37% power.