The study of computing is split at an early stage between the separate branches that deal with hardware and software; there is also a corresponding split in later professional specialisation. This paper explores the essential unity of the two branches and attempts to point to a common framework within which hardware-software codesigns can be expressed as a single executable specification, reasoned about, and transformed into implementations. We also describe a hardware/software co-design environment which has been built, and we show how designs can be realised within this environment. A rapid development cycle is achieved by using FPGAs to host the hardware components of the system. The architecture of a hardware platform for supporting experimental hardware/software co-designs is presented. A particular example of a real-time video processing application built using this design environment is also described. 1 Introduction. Our approach to unifying the traditionally separate discipli...

We present a simple model for specifying and optimising designs which contain elements that can be reconfigured at run-time. In this model the control mechanism for reconfiguration can be implemented in many ways: by the user using multiplexers or other logic blocks, or by FPGAs which support dynamic partial reconfiguration. The model can be used for encoding layout information and for assessing tradeoffs in circuit speed, design size, reconfiguration time, complexity of reconfiguration controller and so on. Our approach is illustrated by various reconfigurable implementations for filtering and locating edges in images. The design tradeoffs of these implementations are being evaluated on a PCI platform, which contains a Xilinx 6216 device. 1

. This paper presents an overview of a prototype hardware compiler which compiles a design expressed in the Ruby language into FPGAs. The features of two important modules, the refinement module and the floorplanning module, are discussed and illustrated. Target code can be produced in various formats, including device-specific formats such as XNF or CFG, and device-independent formats such as VHDL. The viability of our floorplanning scheme is demonstrated by a compiler backend for Algotronix's CAL1024 FPGAs. The implementation of a priority queue is used to illustrate our approach. 1 Introduction Compiling selected parts of application programs into hardware, such as FPGAs, has recently attracted much interest. This method holds promise of producing better special-purpose systems more rapidly than existing techniques. A number of hardware compilers (see, for example, [8], [11]) have been developed for designs described in various languages into hardware netlists, which can then be ma...

FPGA-based systems are a significant area of computing, providing a high-performance implementation substrate for many different applications. However, the key to harnessing their power for most domains is developing mapping tools for automatically transforming a circuit or algorithm into a configuration for the system. In this paper we review the current state-of-the-art in mapping tools for FPGA-based systems, including single-chip and multi-chip mapping algorithms for FPGAs, software support for reconfigurable computing, and tools for run-time reconfigurability. We also discuss the challenges for the future, pointing out where development is still needed to let reconfigurable systems achieve all of their promise. 1.0 Introduction Reconfigurable computing is becoming a powerful methodology for achieving high-performance implementations of many applications. By mapping applications into FPGA hardware resources, extremely efficient computations can be performed. In [Hauck98] w...

The problem of synthesis of gate-level descriptions of digital circuits from behavioural specifications written in higherlevel programming languages (hardware compilation) has been studied for a long time yet a definitive solution has not been forthcoming. The argument of this essay is mainly methodological, bringing a perspective that is informed by recent developments in programming-language theory. We argue that one of the major obstacles in the way of hardware compilation becoming a useful and mature technology is the lack of a well defined function interface model, i.e. a canonical way in which functions communicate with arguments. We discuss the consequences of this problem and propose a solution based on new developments in programming language theory. We conclude by presenting a prototype implementation and some examples illustrating our principles. 1.

. This paper continues our investigation into the feasibility of exploiting the structure of a parallel program to guide its hardware implementation. We review previous work, and present our new approach to the problem based upon placing netlists hierarchically. It is found that appropriate constraints can be derived from the source code in a straight-forward way, and this information can be used to guide the subsequent placement routines. Comparisons with traditional placement procedures based on simulated annealing are given. 1 Introduction The ability to compile programs written in a language such as occam with well-defined semantics and transformation rules facilitates the development of provably-correct systems. By compiling such programs into hardware, we can extend this verifiability to cover systems containing both hardware and software. We have been investigating methods for compiling parallel programs into hardware, using FPGAs as our target technology [1, 2]. One of our goa...

this document which have been, and continue to be, a genuinely inter-disciplinary collaborative venture. In addition, Tony Hoare and Bob McLatchie have been strongly supportive of this work in every way, Bernard Sufrin has provided us with much help on the use of Standard ML, Richard Bird has contributed new algorithms for shared expression extraction, Mark Josephs and Jelio Yantchev have provided useful input on asynchronous models and routing networks. References

We present two new ways to implement ordinary programs with logic gates. One, like imperative programs, has an associated memory to store state; the other, like functional programs, passes the state from one component to the next. Application-specific circuit design can be done more effectively by using a standard programming language to describe the function that a circuit is intended to perform, rather than by describing a circuit that is intended to perform that function. The resulting circuits are produced automatically; they behave according to the programs, and have the same structure as the programs. For timing we use local delays, rather than a global clock or local handshaking. We give a formal semantics for both programs and circuits in order to prove our circuits correct. By simulation, we also demonstrate that the circuits perform favorably compared to others. 1 Introduction The design methods for digital circuits that are commonly found in current textbooks r...