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17
Symbolic model checking for sequential circuit verification
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 1994
"... The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDD’s) [7] and partitioned trunsirion relations [lo], 1111. Because this representation captures some of the regularity in the state space of circuit ..."
Abstract

Cited by 239 (11 self)
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The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDD’s) [7] and partitioned trunsirion relations [lo], 1111. Because this representation captures some of the regularity in the state space of circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5 x 10^120 states. Our model checking algorithm handles full CTL with fairness constraints. Consequently, we are able to express a number of important liveness and fairness properties, which would otherwise not be expressible in CTL. We give empirical results on the performance of the algorithm applied to both synchronous and asynchronous circuits with data path logic.
Multiway Decision Graphs for Automated Hardware Verification
, 1996
"... Traditional ROBDDbased methods of automated verification suffer from the drawback that they require a binary representation of the circuit. To overcome this limitation we propose a broader class of decision graphs, called Multiway Decision Graphs (MDGs), of which ROBDDs are a special case. With MDG ..."
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Cited by 80 (14 self)
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Traditional ROBDDbased methods of automated verification suffer from the drawback that they require a binary representation of the circuit. To overcome this limitation we propose a broader class of decision graphs, called Multiway Decision Graphs (MDGs), of which ROBDDs are a special case. With MDGs, a data value is represented by a single variable of abstract type, rather than by 32 or 64 boolean variables, and a data operation is represented by an uninterpreted function symbol. MDGs are thus much more compact than ROBDDs, and this greatly increases the range of circuits that can be verified. We give algorithms for MDG manipulation, and for implicit state enumeration using MDGs. We have implemented an MDG package and provide experimental results.
BorderBlock Triangular Form and Conjunction Schedule in Image Computation
 in Formal Methods in ComputerAided Design
, 2000
"... . Conjunction scheduling in image computation consists of clustering the parts of a transition relation and ordering the clusters, so that the size of the BDDs for the intermediate results of image computation stay small. We present an approach based on the analysis and permutation of the depende ..."
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Cited by 38 (6 self)
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. Conjunction scheduling in image computation consists of clustering the parts of a transition relation and ordering the clusters, so that the size of the BDDs for the intermediate results of image computation stay small. We present an approach based on the analysis and permutation of the dependence matrix of the transition relation. Our algorithm computes a borderedblock lower triangular form of the matrix that heuristically minimized the active lifetime of variables, that is, the number of conjunctions in which the variables participate. The ordering procedure guides a clustering algorithm based on the affinity of the transition relation parts. The ordering procedure is then applied again to define the cluster conjunction schedule. Our experimental results show the effectiveness of the new algorithm. 1 Introduction Symbolic algorithms for model checking [11] spend most of the time computing the predecessors or successors of sets of states. The algorithms for these image ...
To Split or to Conjoin: The Question in Image Computation
 DAC 2000
, 2000
"... Image computation is the key step in fixpoint computations that are extensively used in model checking. Two techniques have been used for this step: one based on conjunction of the terms of the transition relation, and the other based on recursive case splitting. We discuss when one technique outper ..."
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Cited by 29 (9 self)
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Image computation is the key step in fixpoint computations that are extensively used in model checking. Two techniques have been used for this step: one based on conjunction of the terms of the transition relation, and the other based on recursive case splitting. We discuss when one technique outperforms the other, and consequently formulate a hybrid approach to image computation. Experimental results show that the hybrid algorithm is much more robust than the "pure" algorithms and outperforms both of them in most cases. Our findings also shed light on the remark of several researchers that splitting is especially effective in approximate reachability analysis.
Approximate reachability don’t cares for CTL model checking
 In Proceedings of the International Conference on ComputerAided Design
, 1998
"... RDCs (Reachability Don’t Cares) can have a dramatic impact on the cost of CTL model checking [18]. Unfortunately, RDCs, being a global property, are often much more difficult to compute than the satisfying set of typical CTL formulas. We address this problem through the use of Approximate Reachabili ..."
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Cited by 16 (11 self)
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RDCs (Reachability Don’t Cares) can have a dramatic impact on the cost of CTL model checking [18]. Unfortunately, RDCs, being a global property, are often much more difficult to compute than the satisfying set of typical CTL formulas. We address this problem through the use of Approximate Reachability Don’t Cares (ARDCs), computed with the algorithms developed for the VERITAS sequential synthesis package [4, 5]. Approximate Reachable states represent an upper bound on the set of true reachable states, and thus a lower bound on the set of unreachable (Don’t Care) states. ARDCs can be 10X to 100X (or much more for very large circuits) cheaper to compute than RDCs, and in some cases have the same dramatic effect on CTL model checking as the real RDCs. We also discuss the application of ARDCs to the problem of exact computation of the RDCs themselves. Experiments on industrial benchmarks show that order of magnitude speedups are possible, and occur frequently. The experimental results presented strongly support our claim that ARDCs play a safe and important way out of a serious dilemma: RDCs are necessary for tractable model checking of many large circuits, but the computation of the RDCs themselves is often intractable. We include, and theoretically justify, significant extensions of the VERITAS algorithms, and show that they can be up to an order of magnitude faster, while computing a virtually identical upper bound. 1
Techniques For Efficient Formal Verification Using Binary Decision Diagrams
, 1995
"... The appeal of automatic formal verification is that it's automatic  minimal human labor and expertise should be needed to get useful results and counterexamples. BDD(binary decision diagram)based approaches have promised to allow automatic verification of complex, real systems. For large cl ..."
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Cited by 15 (0 self)
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The appeal of automatic formal verification is that it's automatic  minimal human labor and expertise should be needed to get useful results and counterexamples. BDD(binary decision diagram)based approaches have promised to allow automatic verification of complex, real systems. For large classes of problems, however, (including many distributed protocols, multiprocessor systems, and network architectures) this promise has yet to be fulfilled. Indeed, the few successes have required extensive time and effort from sophisticated researchers in the field. Clearly, techniques are needed that are more sophisticated than the obvious direct implementation of theoretical results. This thesis addresses that need, emphasizing an application domain that has been particularly difficult for BDDbased methods  highlevel models of systems or distributed protocols  rather than gatelevel descriptions of circuits. Additionally, the emphasis is on providing useful debugging information for the...
Cyclebased Symbolic Simulation of Gate Level Synchronous Circuits
, 1999
"... Symbolic methods are often considered the stateoftheart technique for validating digital circuits. Due to their complexity and unpredictable runtime behavior, however, their potential is currently limited to smalltomedium circuits. Logic simulation privileges capacity, it is nicely scalable, f ..."
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Cited by 12 (3 self)
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Symbolic methods are often considered the stateoftheart technique for validating digital circuits. Due to their complexity and unpredictable runtime behavior, however, their potential is currently limited to smalltomedium circuits. Logic simulation privileges capacity, it is nicely scalable, flexible, and it has a predictable runtime behavior. For this reason, it is the common choice for validating large circuits. Simulation, however, typically visits only a small fraction of the state space: The discovery of bugs heavily relies on the expertise of the designer of the test stimuli. In this paper we consider a symbolic simulation approach to the validation problem. Our objective is to tradeoff between formal and numerical methods in order to simulate a circuit with a "very large number" of input combinations and sequences in parallel. We demonstrate larger capacity with respect to symbolic techniques and better efficiency with respect to cyclebased simulation. We show that it is possible to symbolically simulate very large trace sets in parallel (over 100 symbolic inputs) for the largest ISCAS benchmark circuits, using 96Mbytes of memory. 1.
Symbolic Topological Sorting with OBDDs
"... We present a symbolic OBDD algorithm for topological sorting which requires O(log² V) OBDD operations. Then we analyze its true runtime for the directed grid graph and show an upper bound of O(log^4 V · log log V). This is the first true runtime analysis of a symbolic OBDD algorithm for a fun ..."
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Cited by 10 (0 self)
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We present a symbolic OBDD algorithm for topological sorting which requires O(log² V) OBDD operations. Then we analyze its true runtime for the directed grid graph and show an upper bound of O(log^4 V · log log V). This is the first true runtime analysis of a symbolic OBDD algorithm for a fundamental graph problem, and it demonstrates that one can hope that the algorithm behaves well for sufficiently structured inputs.
Partitioning Transition Relations Efficiently and Automatically
, 1995
"... Multiway Decision Graphs (MDGs) have been recently proposed as an efficient representation of Extended Finite State Machines (EFSMs), suitable for automatic hardware verification of Register Transfer Level (RTL) designs [7, 14]. We report here on the results of our research into automatic partitioni ..."
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Cited by 1 (1 self)
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Multiway Decision Graphs (MDGs) have been recently proposed as an efficient representation of Extended Finite State Machines (EFSMs), suitable for automatic hardware verification of Register Transfer Level (RTL) designs [7, 14]. We report here on the results of our research into automatic partitioning of state transition relations described using MDGs. The objective is to achieve the maximum possible performance during an abstract implicit state enumeration procedure that is at the basis of our automatic verification method. 1 Introduction Bryant's Reduced Ordered Binary Decision Diagrams (ROBDDs) [2] have proved to be a powerful tool for automated hardware verification [3, 4, 6, 8, 13]. ROBDDs have a drawback, however, when verifying hardware designs at higher levels of abstraction, such as the RegisterTransfer Level: They require a binary representation of the entire circuit including the datapath operations, and the size of the corresponding ROBDDs can grow, sometimes exponential...
Microsoft
"... We study the problem of optimizing synchronous sequential circuits. There have been previous efforts to optimize such circuits. However, all previous attempts make implicit or explicit assumptions about the design or the environment of the design. For example, it is widespread practice to assume the ..."
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We study the problem of optimizing synchronous sequential circuits. There have been previous efforts to optimize such circuits. However, all previous attempts make implicit or explicit assumptions about the design or the environment of the design. For example, it is widespread practice to assume the existence of a hardware reset line and consequently a fixed powerup state; in the absence of the same, a common premise is that the design’s environment will apply an initializing sequence. We review the concept of safe replaceability which does away with these assumptions and the delaysafe replaceability notion, which is applicable when the design’s output is not used for a certain number of cycles after powerup. We then develop procedures for optimizing the combinational nextstate and output logic, as well as routines for reencoding the state space and removing state bits under these replaceability criteria. Experimental results demonstrate the effectiveness of our algorithms. Categories and Subject Descriptors: B.6.3 [Logic Design]: Design aids—Automatic synthesis