Results 1 
9 of
9
Errortracer: Design error diagnosis based on fault simulation techniques
 IEEE Trans. CAD
, 1999
"... Abstract—This paper addresses the problem of locating error sources in an erroneous combinational or sequential circuit. We use a fault simulationbased technique to approximate each internal signal’s correcting power. The correcting power of a particular signal is measured in terms of the signal’s ..."
Abstract

Cited by 19 (0 self)
 Add to MetaCart
(Show Context)
Abstract—This paper addresses the problem of locating error sources in an erroneous combinational or sequential circuit. We use a fault simulationbased technique to approximate each internal signal’s correcting power. The correcting power of a particular signal is measured in terms of the signal’s correctable set, namely, the maximum set of erroneous input vectors or sequences that can be corrected by resynthesizing the signal. Only the signals that can correct every given erroneous input vector or sequence are considered as a potential error source. Our algorithm offers three major advantages over existing methods. First, unlike symbolic approaches, it is applicable for large circuits. Second, it delivers more accurate results than other simulationbased approaches because it is based on a more stringent condition for identifying potential error sources. Third, it can be generalized to identify multiple errors theoretically. Experimental results on diagnosing combinational and sequential circuits with one and two random errors are presented to show the effectiveness and efficiency of this new approach. Index Terms—Design automation, error correction, fault diagnosis, simulation. I.
Design Error Diagnosis in Sequential Circuits
 Proc. Correct Hardware Design and Verification Methods, CHARME'95, Lecture
, 1995
"... . We present a new diagnostic algorithm for localising design errors in sequential circuits. The specification and the implementation may have different number of state variables, and different state encoding. The algorithm is based on the new concept of possible next states describing the possible ..."
Abstract

Cited by 11 (4 self)
 Add to MetaCart
(Show Context)
. We present a new diagnostic algorithm for localising design errors in sequential circuits. The specification and the implementation may have different number of state variables, and different state encoding. The algorithm is based on the new concept of possible next states describing the possible states of the circuit due to the existence of the error. Results obtained on benchmark circuits show that the error is always found, with an execution time proportional to the product of the circuit size, and the length of the test sequences used. 1 Introduction Although automated design tools are routinely used for digital circuits synthesis, manual changes are still being done to improve the performance, to obtain more compact structures, or to carry on small specification changes; doing so, the insertion of an unintentional error is very likely to happen. Another source of design errors is the presence of software bugs in the automated design and optimization tools. Therefore, formal ve...
FaultSimulation Based Design Error Diagnosis for Sequential Circuits
 in Proc. ACM/IEEE Design Automation Conf
, 1998
"... This paper addresses the problem of locating design errors in a sequential circuit. For singleerror circuits, we consider a signal f as a potential error source only if the circuit can be completely rectified by resynthesizing f (i.e., changing the function of signal f). In order to handle larger ..."
Abstract

Cited by 7 (1 self)
 Add to MetaCart
(Show Context)
This paper addresses the problem of locating design errors in a sequential circuit. For singleerror circuits, we consider a signal f as a potential error source only if the circuit can be completely rectified by resynthesizing f (i.e., changing the function of signal f). In order to handle larger circuits, we do not rely on Binary Decision Diagram. Instead, we search for potential error sources by a modified sequential fault simulation process. The main contributions of this paper are twofold: (1) we derive the necessary and sufficient condition of whether an erroneous input sequence (i.e., an input sequence producing erroneous responses) can be corrected by changing the function of a particular internal signal; and (2) we propose a modified fault simulation procedure to check this condition. Our approach does not rely on any error model, and thus, is suitable for general types of errors. Furthermore, it can be easily extended to identify multiple errors. Experimental...
Engineering change in a nondeterministic fsm setting
 In Proceedings of IEEE/ACM Design Automation Conference
, 1996
"... personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is ..."
Abstract

Cited by 5 (1 self)
 Add to MetaCart
(Show Context)
personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is
Efficient Functional Diagnosis For Synchronous Sequential Circuits Based On And/or Graphs
 Proceedings of Int'l Symposium on IC Technologies, systems and Applications
, 1997
"... In this paper we present a new model for diagnosis of errors in Synchronous Sequential Circuits (SCC) on the functional level. In contrast to many previously published approaches we do not consider a specific implementation. Instead we use tests based on the transition behavior of the corresponding ..."
Abstract

Cited by 2 (2 self)
 Add to MetaCart
(Show Context)
In this paper we present a new model for diagnosis of errors in Synchronous Sequential Circuits (SCC) on the functional level. In contrast to many previously published approaches we do not consider a specific implementation. Instead we use tests based on the transition behavior of the corresponding Finite State Machine (FSM). Thus, the approach can be used for verification and test. We describe a method for constructing a minimal cost test based on AND/OR graphs. Exact and heuristic methods are presented. First experimental results for randomly generated FSMs are given that demonstrate the efficiency of our approach. 1 Introduction Nowadays, circuit design is becoming more and more complex. Thus, the error probability also increases. Since timetomarket aspects are increasingly important it is desirable to detect errors as early as possible. Additionally, this also reduces the production costs. For this, nowadays CAD tools should also support features for error diagnosis, i.e. error...
Sequential Logic Rectifications with Approximate SPFDs
"... In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential circuits are hard to perform due to the vast underlying solution space. This paper proposes an SPFDbased sequential logic ..."
Abstract

Cited by 1 (1 self)
 Add to MetaCart
(Show Context)
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential circuits are hard to perform due to the vast underlying solution space. This paper proposes an SPFDbased sequential logic transformation methodology to tackle the problem with no sacrifice on performance. It first presents an efficient approach to construct approximate SPFDs (aSPFDs) for sequential circuits. Then, it demonstrates an algorithm using aSPFDs to perform the desirable sequential logic transformations using both combinational and sequential don’t cares. Experimental results show the effectiveness and robustness of the approach. 1.
An Engineering Change Methodology using Simulation Relations
"... Abstract In this paper, we address the problem of Engineering Change in a nondeterministic finite state machine framework. We are given a deterministic implementation FSM, and a nondeterministic specification FSM, such that the implementation does not meet the specification. The problem consists o ..."
Abstract
 Add to MetaCart
(Show Context)
Abstract In this paper, we address the problem of Engineering Change in a nondeterministic finite state machine framework. We are given a deterministic implementation FSM, and a nondeterministic specification FSM, such that the implementation does not meet the specification. The problem consists of controlling the implementation FSM in such a way that for all possible sequences of external inputs, the generated outputs are allowed in the specification. We propose a new formalism for the Engineering Change problem which is applicable to nondeterministic specifications. We use the notion of Simulation Relations from the theory of concurrent systems, to develop this new formalism. Our method is cast in the form of a simulation of the implementation by the specification. We prove the necessary and sufficient condition for the existence of a solution to the problem. We also provide an algorithm to obtain all possible solutions under this setting. We have implemented this algorithm, using implicit state enumeration and Reduced Ordered Binary Decision Diagrams (ROBDDs). An important feature of our method is that the algorithm gives us a solution which is correct by construction, and accordingly we do not need to perform a separate verification step in the design. 2
Automating Logic Transformations with Approximate SPFDs
"... During the VLSI design process, a synthesized design is often required to be modified in order to accommodate different goals. To preserve the engineering effort already invested, designers seek small logic structural transformations to achieve these logic restructuring goals. This paper proposes a ..."
Abstract
 Add to MetaCart
During the VLSI design process, a synthesized design is often required to be modified in order to accommodate different goals. To preserve the engineering effort already invested, designers seek small logic structural transformations to achieve these logic restructuring goals. This paper proposes a systematic methodology to devise such transformations automatically. It first presents a simulationbased formulation to approximate SPFDs and avoid the memory/time explosion issue inherent with the original representation. Then it uses this new data structure to devise the required transformations dynamically without the need of a static dictionary model. The methodology is applied to both combinational and sequential designs with transformations at a single or multiple locations. An extensive suite of experiments documents the benefits of the proposed methodology when compared to existing practices.
A Redesign Technique for Combinational Circuits Based on Gate Reconnections
 In Proc. of the Intl. Conf. on ComputerAided Design
, 1994
"... In this paper, we consider a redesign technique applicable to combinational circuits implemented with gatearray or standardcell technology, where we rectify an existing circuit only by reconnecting gates on the circuit with all the gate types unchanged. This constraint allows us to reuse the origi ..."
Abstract
 Add to MetaCart
In this paper, we consider a redesign technique applicable to combinational circuits implemented with gatearray or standardcell technology, where we rectify an existing circuit only by reconnecting gates on the circuit with all the gate types unchanged. This constraint allows us to reuse the original placement as is, thereby speeding up the total time needed for a redesign. We formulate this problem as a Booleanconstraint problem and give a BDDbased algorithm to check the feasibility of redesign. 1 Introduction Incremental synthesis is a synthesis technique which reuses existing circuits to come up with circuits satisfying new specifications. Since engineering changes arise frequently in actual design processes, the technique is of practical importance from an industrial point of view. Several synthesis techniques have already been proposed for combinational circuits [2, 3, 9, 8] and sequential circuits [1], where an additional logic is attached before and/or after an existing ci...