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Digital Circuit Optimization via Geometric Programming
 Operations Research
, 2005
"... informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently s ..."
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Cited by 38 (7 self)
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informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistorcapacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.
A broadband noisecanceling CMOS LNA for 3.1–10.6GHz UWB receiver
 in Proc. IEEE Custom Integrated Circuits Conf
, 2005
"... Abstract—An ultrawideband 3.1–10.6GHz lownoise amplifier employing a broadband noisecanceling technique is presented. By using the proposed circuit and design methodology, the noise from the matching device is greatly suppressed over the desired UWB band, while the noise from other devices perfo ..."
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Cited by 14 (1 self)
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Abstract—An ultrawideband 3.1–10.6GHz lownoise amplifier employing a broadband noisecanceling technique is presented. By using the proposed circuit and design methodology, the noise from the matching device is greatly suppressed over the desired UWB band, while the noise from other devices performing noise cancellation is minimized by the systematic approach. Fabricated in a 0.18 m CMOS process, the IC prototype achieves a power gain of 9.7 dB over a 3 dB bandwidth of 1.2–11.9GHz and a noise figure of 4.5–5.1 dB in the entire UWB band. It consumes 20 mW from a 1.8V supply and occupies an area of only 0.59 mm2. Index Terms—Broadband, lownoise amplifier (LNA), noise canceling, ultrawideband (UWB). I.
Bandwidth enhancement for transimpedance amplifier
 IEEE JSSC
, 2004
"... Abstract—A technique for bandwidth enhancement of a given amplifier is presented. Adding several interstage passive matching networks enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed int ..."
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Cited by 10 (2 self)
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Abstract—A technique for bandwidth enhancement of a given amplifier is presented. Adding several interstage passive matching networks enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed into passive networks. A simplified design procedure, using wellknown lowpass filter component values, is introduced. To demonstrate the feasibility of the method, a CMOS transimpedance amplifier (TIA) is implemented in a 0.18 m BiCMOS technology. It achieves 3 dB bandwidth of 9.2 GHz in the presence of a 0.5pF photodiode capacitance. This corresponds to a bandwidth enhancement ratio of 2.4 over the amplifier without the additional passive networks. The transresistance gain is 54 dB, while drawing 55 mA from a 2.5V supply. The input sensitivity of the TIA is 18 dBm for a bit error rate of
EQUALIZERS FOR HIGHSPEED SERIAL LINKS
, 2005
"... In this tutorial paper we present equalization techniques to mitigate intersymbol interference (ISI) in highspeed communication links. Both transmit and receive equalizers are analyzed and highspeed circuits implementing them are presented. It is shown that a digital transmit equalizer is the sim ..."
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Cited by 4 (2 self)
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In this tutorial paper we present equalization techniques to mitigate intersymbol interference (ISI) in highspeed communication links. Both transmit and receive equalizers are analyzed and highspeed circuits implementing them are presented. It is shown that a digital transmit equalizer is the simplest to design, while a continuoustime receive equalizer generally provides better performance. Decision feedback equalizer (DFE) is described and the loop latency problem is addressed. Finally, techniques to set the equalizer parameters adaptively are presented.
Broadband design techniques for transimpedance amplifiers
 IEEE Trans. Circuits Syst. I, Reg. Papers
, 2007
"... Abstract—In this paper, a novel bandwidth enhancement technique based on the combination of capacitive degeneration, broadband matching network, and the regulated cascode (RGC) input stage is proposed and analyzed, which turns the transimpedance amplifier (TIA) design into a fifthorder lowpass f ..."
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Cited by 3 (0 self)
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Abstract—In this paper, a novel bandwidth enhancement technique based on the combination of capacitive degeneration, broadband matching network, and the regulated cascode (RGC) input stage is proposed and analyzed, which turns the transimpedance amplifier (TIA) design into a fifthorder lowpass filter with Butterworth response. This broadband design methodology for TIAs is presented with an example implemented in CHRT 0.18 m 1.8V RF CMOS technology. Measurement data shows a 3dB bandwidth of about 8 GHz with 0.25pF photodiode capacitance. Comparing with the core RGC TIA without capacitive degeneration and broadband matching network, this design achieves an overall bandwidth enhancement ratio of 3.6 with very small gain ripple. The transimpedance gain is 53 dB with a group delay of 80 20 ps. The chip consumes only 13.5mW dc power and the measured average inputreferred noise current spectral density is 18 pA / Hz up to 10 GHz. Index Terms—Bandwidth enhancement, broadband, matching network, regulated cascode (RGC), transimpedance amplifier (TIA). I.
A Heuristic Method for Statistical Digital Circuit Sizing
"... In this paper we give a brief overview of a heuristic method for approximately solving a statistical digital circuit sizing problem, by reducing it to a related deterministic sizing problem that includes extra margins in each of the gate delays to account for the variation. Since the method is based ..."
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Cited by 2 (1 self)
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In this paper we give a brief overview of a heuristic method for approximately solving a statistical digital circuit sizing problem, by reducing it to a related deterministic sizing problem that includes extra margins in each of the gate delays to account for the variation. Since the method is based on solving a deterministic sizing problem, it readily handles largescale problems. Numerical experiments show that the resulting designs are often substantially better than one in which the variation in delay is ignored, and often quite close to the global optimum. Moreover, the designs seem to be good despite the simplicity of the statistical model (which ignores gate distribution shape, correlations, and so on). We illustrate the method on a 32bit LadnerFischer adder, with a simple resistorcapacitor (RC) delay model, and a Pelgrom model of delay variation.
A LowPower 26GHz TransformerBased Regulated Cascode SiGe BiCMOS Transimpedance Amplifier
 IEEE Journal of SolidState Circuits
, 2013
"... Abstract — A 26 GHz transimpedance amplifier (TIA) with transformerbased regulated cascode (RGC) input stage is proposed and analyzed. The transformer enhances the effective transconductance of the TIA’s input commonbase transistor; reducing the input resistance and providing considerable bandwid ..."
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Abstract — A 26 GHz transimpedance amplifier (TIA) with transformerbased regulated cascode (RGC) input stage is proposed and analyzed. The transformer enhances the effective transconductance of the TIA’s input commonbase transistor; reducing the input resistance and providing considerable bandwidth extension. The TIA is implemented in a 0.25µm BiCMOS technology. Measurement shows the singleended transimpedance gain of 53dBΩ with3dB bandwidth of 26 GHz. Total chip power, including an output buffer, is 28.2mW from a 2.5V supply; while core TIA power is 8.2mW. The measured average inputreferred noise current spectral density is 21.3 /√. Total chip area, including pads, is 960µm×780µm.
H.Yoo, “CMOS Optical Receiver Chipset for Gigabit Ethernet Applications
 IEEE International Symposium on Circuits and Systems
, 2003
"... This paper describes a 1.25Gb/s simplified CMOS optical receiver chipset for Gigabit Ethernet applications, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit. The TIA takes a fully differential regulated cascode configuration, demonstrating 700MHz bandwidth ..."
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This paper describes a 1.25Gb/s simplified CMOS optical receiver chipset for Gigabit Ethernet applications, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit. The TIA takes a fully differential regulated cascode configuration, demonstrating 700MHz bandwidth for 1pF photodiode capacitance, 80dBΩ transimpedance gain,17dBm sensitivity for BER of 1012, and 27mW power consumption. In our design, the postamplifier is omitted due to the large voltage swing of the TIA and to the high sensitivity of the proposed CDR. The CDR takes a halfrate clock technique and thus removes the necessity of a 1:2 demultiplexer. It achieves 40mVpp sensitivity due to the high sensitivity phase detector. The RMS clock jitter and data jitter are measured to be 3.9psrms and 20.2psrms, respectively. Two chips dissipate 127mW from a single 2.5V supply. 1.
Analysis and Design of Wideband CMOS Transimpedance Amplifiers Using Inductive Feedback
, 2012
"... 2012 © Omidreza Ghasemi, 2012 ii CONCORDIA UNIVERSITY ..."
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Experimental Results for an Inductively Matched Microwave Amplifier in a Standard 0.5 Micron CMOS Process Using Four Identical Spiral Inductors
"... to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to ..."
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to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to