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Timing Verification by Successive Approximation
 INFORMATION AND COMPUTATION
, 1995
"... We present an algorithm for verifying that a model M with timing constraints satisfies a given temporal property T . The model M is given as a parallel composition of !automata P i , where each automaton P i is constrained by bounds on delays. The property T is given as an !automaton as well, and ..."
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Cited by 44 (11 self)
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We present an algorithm for verifying that a model M with timing constraints satisfies a given temporal property T . The model M is given as a parallel composition of !automata P i , where each automaton P i is constrained by bounds on delays. The property T is given as an !automaton as well, and the verification problem is posed as a language inclusion question L(M ) ` L(T ). In constructing the composition M of the constrained automata P i , one needs to rule out the behaviors that are inconsistent with the delay bounds, and this step is (provably) computationally expensive. We propose an iterative solution which involves generating successive approximations M j to M , with containment L(M ) ` L(M j ) and monotone convergence L(M j ) ! L(M ) within a bounded number of steps. As the succession progresses, the approximations M j become more complex. At any step of the iteration one may get a proof or a counterexample to the original language inclusion question. The described algori...
Efficient reachability analysis of hierarchical reactive machines
 INTERNATIONAL CONFERENCE ON COMPUTERAIDED VERIFICATION
, 2000
"... Hierarchical state machines is a popular visual formalism for software specifications. To apply automated analysis to such specifications, the traditional approach is to compile them to existing model checkers. Aimed at exploiting the modular structure more effectively, our approach is to develop al ..."
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Cited by 23 (5 self)
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Hierarchical state machines is a popular visual formalism for software specifications. To apply automated analysis to such specifications, the traditional approach is to compile them to existing model checkers. Aimed at exploiting the modular structure more effectively, our approach is to develop algorithms that work directly on the hierarchical structure. First, we report on an implementation of a visual hierarchical language with modular features such as nested modes, variable scoping, mode reuse, exceptions, group transitions, and history. Then, we identify a variety of heuristics to exploit these modular features during reachability analysis. We report on an enumerative as well as a symbolic checker, and case studies.
From church and prior to psl
 In O. Grumberg & H. Veith (Eds.), 25 Years of Model Checking
, 2008
"... Abstract. One of the surprising developments in the area of program verification is how ideas introduced originally by logicians in the 1950s ended up yielding by 2003 an industrialstandard propertyspecification language called PSL. This development was enabled by the equally unlikely transformati ..."
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Cited by 7 (0 self)
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Abstract. One of the surprising developments in the area of program verification is how ideas introduced originally by logicians in the 1950s ended up yielding by 2003 an industrialstandard propertyspecification language called PSL. This development was enabled by the equally unlikely transformation of the mathematical machinery of automata on infinite words, introduced in the early 1960s for secondorder arithmetics, into effective algorithms for modelchecking tools. This paper attempts to trace the tangled threads of this development.
From Monadic Logic to PSL
, 2007
"... One of the surprising developments in the area of program verification is how ideas introduced originally by logicians in the 1950s ended up yielding by 2003 an industrialstandard propertyspecification language called PSL. This development was enabled by the equally unlikely transformation of the ..."
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Cited by 3 (1 self)
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One of the surprising developments in the area of program verification is how ideas introduced originally by logicians in the 1950s ended up yielding by 2003 an industrialstandard propertyspecification language called PSL. This development was enabled by the equally unlikely transformation of the mathematical machinery of automata on infinite words, introduced in the early 1960s for secondorder arithmetics, into effective algorithms for modelchecking tools. This paper attempts to trace the tangled threads of this development.
From
"... Abstract. One of the surprising developments in the area of program verificationis how ideas introduced originally by logicians in the 1950s ended up yielding by 2003 an industrialstandard propertyspecification language called PSL. Thisdevelopment was enabled by the equally unlikely transformation ..."
Abstract
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Abstract. One of the surprising developments in the area of program verificationis how ideas introduced originally by logicians in the 1950s ended up yielding by 2003 an industrialstandard propertyspecification language called PSL. Thisdevelopment was enabled by the equally unlikely transformation of the mathematical machinery of automata on infinite words, introduced in the early 1960sfor secondorder arithmetics, into effective algorithms for modelchecking tools. This paper attempts to trace the tangled threads of this development. 1 Thread I: Classical Logic of Time 1.1 Reasoning about Sequential Circuits The field of hardware verification seems to have been started in a little known 1957paper by Alonzo Church, 19031995, in which he described the use of logic to specify sequential circuits [24]. A sequential circuit is a switching circuit whose output dependsnot only upon its input, but also on what its input has been in the past. A sequential circuit is a particular type of finitestate machine, which became a subject of study inmathematical logic and computer science in the 1950s. Formally, a sequential circuit C = (I, O, R, f, g, r0) consists of a finite set I ofBoolean input signals, a finite set O of Boolean output signals, a finite set R of Booleansequential elements, a transition function f: 2I * 2R! 2R, an output function g:2 R! 2O, and an initial state r0 2 2R. (We refer to elements of I [ O [ R as circuit elements, and assume that I, O, and R are disjoint.) Intuitively, a state of the circuit is aBoolean assignment to the sequential elements. The initial state is r0. In a state r 2 2R,the Boolean assignment to the output signals is g(r). When the circuit is in state r 2 2Rand it reads an input assignment i 2 2I, it changes its state to f (i, r).A trace over a set V of Boolean variables is an infinite word over the alphabet 2V,i.e., an element of (2 V)!. A trace of the sequential circuit C is a trace over I [ O [ R that satisfies some conditions. Specifically, a sequence o / = (i0, r0, o0), (i1, r1, o1),...,where i