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Congestion Prediction in Early Stages of Physical Design CHIUWING SHAM
"... Routability optimization has become a major concern in physical design of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominant factor of the overall performance of a circuit. In order to optimize interconnect cost, we need a good congestion estimation meth ..."
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Routability optimization has become a major concern in physical design of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominant factor of the overall performance of a circuit. In order to optimize interconnect cost, we need a good congestion estimation method to predict routability in the early designing stages. Many congestion models have been proposed but there’s still a lot of room for improvement. Besides, routers will perform ripup and reroute operations to prevent overflow, but most models do not consider this case. The outcome is that the existing models will usually underestimate the routability. In this paper, we have a comprehensive study on our proposed congestion models. Results show that the estimation results of our approaches are always more accurate than the previous congestion models.
A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk
 Noise,” Proceedings of the International Conference on VLSI Design
, 2006
"... Abstract — In this paper, we propose a new methodology for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise in deep submicron VLSI circuits. The wire sizing problem is modeled as an optimization problem formulated as a normal form game and solved using the Nash eq ..."
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Abstract — In this paper, we propose a new methodology for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise in deep submicron VLSI circuits. The wire sizing problem is modeled as an optimization problem formulated as a normal form game and solved using the Nash equilibrium. Game theory allows the optimization of multiple metrics with conflicting objectives. This property is exploited in modeling the wire sizing problem while simultaneously optimizing interconnect delay and crosstalk noise, which are conflicting in nature. The nets connecting the driving cell and the driven cell are divided into net segments. The net segments within a channel are modeled as players, the range of possible wire sizes forms the set of strategies and the payoff function is derived as the geometric mean of interconnect delay and crosstalk noise. The net segments are optimized from the ones closest to the driven cell towards the ones at the driving cell. The complete information about the coupling effects among the nets is extracted after the detailed routing phase. The resulting algorithm for wire sizing is linear in terms of the number of wire segments in the given circuit. Experimental results on several medium and large open core designs indicate that the proposed algorithm yields an average reduction of 21.48 % in interconnect delay and 26.25 % in crosstalk noise over and above the optimization from the Cadence place and route tools without any area overhead. The algorithm performs significantly better than simulated annealing and genetic search as established through experimental results. A mathematical proof of existence for Nash equilibrium solution for the proposed wire sizing formulation is provided. I.
Graph theoretical problems in next generation chip design
, 2003
"... A major component of computer chip design is creating an optimal physical layout of a netlist, i.e., determining where to place the functional elements and how to route the wires connecting them when manufacturing a chip. Because of its basic structure, the overall problem of netlist layout contains ..."
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Cited by 2 (1 self)
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A major component of computer chip design is creating an optimal physical layout of a netlist, i.e., determining where to place the functional elements and how to route the wires connecting them when manufacturing a chip. Because of its basic structure, the overall problem of netlist layout contains many questions that lend themselves to graph theoretical modeling and analysis. We will describe the basic principles of netlist layout and present several graph theoretical questions inherent in the problem. Possible approaches to these questions include concepts from hypergraphs, graph partitioning, graph drawing, graph and geometric thickness, tree width, grid graphs, planar embeddings, and geometric graph theory.
Area reduction on interconnect optimized floorplan using deadspace utilization
 In Proceedings of the IEEE International Midwest Symposium on Circuits and Systems. I445–I448
, 2004
"... Abstract — Interconnect optimization has become the major concern in floorplanning. Many approaches would use simulated annealing (SA) with a cost function composed of a weighted sum of the area, wirelength and interconnect cost. These approaches can reduce the interconnect cost efficiently but th ..."
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Abstract — Interconnect optimization has become the major concern in floorplanning. Many approaches would use simulated annealing (SA) with a cost function composed of a weighted sum of the area, wirelength and interconnect cost. These approaches can reduce the interconnect cost efficiently but the area penalty of the interconnect optimized floorplan is large. In this paper, we propose a new approach to reduce the area of interconnect optimized floorplan using deadspace utilization (DSU) by linear programming. The modules can be simple rectilinear shaped like Lshaped and Tshaped in floorplanning. Thus, some deadspace can be redistributed to the modules and the area of modules can be expanded. If the area of all the modules can be expanded by a same ratio using deadspace utilization, it means that the whole floorplan can be compacted by the same ratio. In addition, we can also limit the compaction ratio to prevent overcongestion. Experiments show that we can apply the deadspace utilization technique to reduce the area and wirelength of the interconnect optimized floorplan further and the constraint of the routability and congestion can be maintained at the same time. A. Motivations I.
Area Reduction by Deadspace Utilization on Interconnect Optimized Floorplan CHIUWING SHAM The Hong Kong Polytechnic University and
"... Interconnect optimization has become the major concern in floorplanning. Many approaches would use simulated annealing (SA) with a cost function composed of a weighted sum of area, wirelength, and interconnect cost. These approaches can reduce the interconnect cost efficiently but the area penalty o ..."
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Interconnect optimization has become the major concern in floorplanning. Many approaches would use simulated annealing (SA) with a cost function composed of a weighted sum of area, wirelength, and interconnect cost. These approaches can reduce the interconnect cost efficiently but the area penalty of the interconnect optimized floorplan is usually quite large. In this article, we propose an approach called deadspace utilization (DSU) to reclaim the unused area of an interconnect optimized floorplan by linear programming. Since modules are not necessarily rectangular in shape in floorplanning, some deadspace can be redistributed to the modules to increase the area occupied by each module. If the area of each module can be expanded by the same ratio, the whole floorplan can be compacted by that ratio to give a smaller floorplan. However, we will limit the compaction ratio to prevent overcongestion. Experiments show that we can apply this deadspace utilization technique to reduce the area and total wirelength of an interconnect optimized floorplan further while the routability can be maintained at the same time.
General Terms: Performance
"... Recent advances in VLSI technology have made optimization of the interconnect delay and routability of a circuit more important. We should consider interconnect planning as early as possible. We propose a postfloorplanning step to reduce the interconnect cost of a floorplan by searching alternative ..."
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Recent advances in VLSI technology have made optimization of the interconnect delay and routability of a circuit more important. We should consider interconnect planning as early as possible. We propose a postfloorplanning step to reduce the interconnect cost of a floorplan by searching alternative packings. If a packing contains a rectangular bounding box of a group of modules, we can rearrange the blocks in the bounding box to obtain a new floorplan with the same area, but possibly with a smaller interconnect cost. Experimental results show that we can reduce the interconnect cost of a packing without any penalty in area.
Graph Drawing for Floorplanning with Flexible Blocks
"... We discuss further development of a modified forcedirected graph drawing placement algorithm for reducing wire length while placing flexible blocks during the floorplanning stage of computer chip design. An effective repelling perimeter allows floorplanning blocks and to pass through each other dur ..."
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We discuss further development of a modified forcedirected graph drawing placement algorithm for reducing wire length while placing flexible blocks during the floorplanning stage of computer chip design. An effective repelling perimeter allows floorplanning blocks and to pass through each other during early stages of a run in response to spring tensions on the edges, yet repel just enough to avoid overlap in later stages. Pressure equalization equations permit flexible blocks to reshape dynamically in reaction to penetration from neighboring blocks. We present a number of experimental results demonstrating the feasibility of this approach, achieving up to 31 % wirelength improvement over commercial tools.
Principles and Preliminary Results for ForceDirected Floorplanning with Malleable Blocks
"... We apply forcedirected graph drawing techniques to the floorplanning process of computer chip design, which is essentially a problem of fitting interconnected rectangles into a prescribed region without overlap. We adapt the forcedirected graph drawing techniques to accommodate the rectangular vert ..."
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We apply forcedirected graph drawing techniques to the floorplanning process of computer chip design, which is essentially a problem of fitting interconnected rectangles into a prescribed region without overlap. We adapt the forcedirected graph drawing techniques to accommodate the rectangular vertices representing chip components by developing a physical model that allows the components to ‘pass through ’ each other and to adjust their aspect ratios as needed while approaching a solution. We provide the underlying mathematics and some preliminary output from a prototype program based on our heuristics. Key words: Floorplanning, netlist layout, spring embedding, forcedirected, graph drawing, geometric graph theory,
InterconnectDriven Floorplanning by Searching Alternative Packings
"... Abstract — In traditional floorplanners, area minimization is an important issue. Due to the recent advances in VLSI technology, the number of transistors in a design and their switching speeds are increasing rapidly. This results in the increasing importance of interconnect delay and routability of ..."
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Abstract — In traditional floorplanners, area minimization is an important issue. Due to the recent advances in VLSI technology, the number of transistors in a design and their switching speeds are increasing rapidly. This results in the increasing importance of interconnect delay and routability of a circuit. We should consider interconnect planning and buffer planning as soon as possible. In this paper, we propose a method to reduce interconnect cost of a floorplan by searching alternative packings. We found that if a floorplan F contains some rectangular supermodules, we can rearrange the blocks in the supermodule to obtain a new floorplan with the same area as F but possibly with a smaller interconnect cost. Experimental results show that we can always reduce the interconnect cost of a floorplan without any penalty in area and runtime by using this method. I.