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Low-power logic styles: CMOS versus pass-transistor logic
- IEEE J. Solid-State Circuits
, 1997
"... Abstract — Recently reported logic style comparisons based on full-adder circuits claimed complementary passtransistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different lo ..."
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Cited by 52 (1 self)
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Abstract — Recently reported logic style comparisons based on full-adder circuits claimed complementary passtransistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangementsdemonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-bit adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits, if low voltage, low power, and small power-delay products are of concern. Index Terms — Adder circuits, CPL, complementary CMOS, low-voltage low-power logic styles, pass-transistor
Circuit Analysis and Design using Evolutionary Algorithms
, 2000
"... This paper focuses on electronic design at circuit level. The use of evolutionary algorithms to this application is discussed and a trade off to existing approaches is investigated. The design and analyzing task at this level is described in detail. As example a 1-bit full adder design in static CMO ..."
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Cited by 2 (0 self)
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This paper focuses on electronic design at circuit level. The use of evolutionary algorithms to this application is discussed and a trade off to existing approaches is investigated. The design and analyzing task at this level is described in detail. As example a 1-bit full adder design in static CMOS is inspected with regard to power consumption and delay. In algorithmic scope both, single- and multi-objective optimization are regarded here. 1 Introduction Development of new concepts to low power design needs a comparison to existing alternatives. Independant of the abstract level an optimal decision in lower, as well as in upper levels is essential to determine the concepts potential. This paper focuses on the circuit level as a parameter adjustment task. Instead of commonly used local meliorating procedure evolutionary algorithms as a global optimum seeking method are used here. A global search could guide the designer to alternative designs far away from usual ones. This becomes m...

