: The sum-product algorithm (belief/probability propagation) can be naturally mapped into analog transistor circuits. These circuits enable the construction of analog-VLSI decoders for turbo codes, low-density parity-check codes, and similar codes. Index Terms: Turbo codes, iterative decoding, factor graphs, belief propagation, analog circuits. The material in this paper was presented in part at the 1998 IEEE Int. Symp. on Information Theory, Cambridge, MA USA, August 16-21, 1998, and at several other conferences. This research was supported by the Swiss National Science Foundation under Grant 21-49619.96. 1 Now with Signal and Information Processing Lab (ISI), ETH Zentrum, CH-8092 Zrich, Switzerland. The work was performed while with Endora Tech AG, Basel. 2 Signal and Information Processing Lab (ISI), ETH Zentrum, CH-8092 Zrich, Switzerland. 3 Now with Globespan Semiconductor Inc., 100 Schulz Drive, Red Bank, NJ 07701. The work was performed while with ISI/ETH Zurich. 4 Endo...

Analog Viterbi decoders are finding widespread use in class-IV partial-response disk-drive applications. These analog realizations are often used because they are smaller and consume less power than their digital counterparts. However, class-IV signaling allows simplifications during Viterbi detection and thus existing analog decoders have limited applications. The purpose of this paper is to develop efficient analog circuits that can be used for general Viterbi detection. To demonstrate the feasibility of the proposed approach, the analog portions of two analog Viterbi decoders were fabricated in a 0.8-m BiCMOS process. With an off-chip digital path memory, operation up to 50 Mb/s is demonstrated. However, simulations indicate that with on-chip digital path memory, speeds on the order of 300 Mb/s can be achieved. The power consumption of the proposed approach is estimated to be 15 mW/state drawn from a single 5-V power supply. Index Terms---Analog, BiCMOS, communications, Viterbi. I...

ACKNOWLEDEGEMENTS First, I’d like to acknowledge my research advisor, Dr. Joy Laskar for his guidance and support for my Ph.D. study. Without his enthusiastic motivations, this work would not be finished as successful as it is. He gave me the sincere and profound lessons for the academic areas as well as the role models to live as a mature human being. I’d also like to appreciate the committee members, Dr. Emmanouil M. Tentzeris, Dr. John Papapolymerou, Dr. Marshall Leach and Dr. Paul Kohl for their efforts and advice for this work. I would like to thank Jim Wiser and Peter Dean in the National Semiconductor Corp. for their support of CMOS fabrication opportunities. I’d like to specially thank Dr. Edward Gebara for the discussions and comments throughout the research work. He and I could come up with so many achievements by leading the mixed signal team in the Microwave Application Group (MAG). I also would like to thank Dr. Changho Lee, Dr. Sangwoo Han, Dr. Kyutae Lim, and Dr. Seungyup Yoo for their helpful comments and guidance for my study and life at Tech. Specifically, if there weren’t their efforts to recommend me to the MAG, I could not even think about this work. I am indebted my colleague members in the MAG for their support. I owe special thanks to the mixed signal team members: Franklin Bien, Soumya Chandramouli,

Analog Viterbi decoders have recently been shown to be viable alternatives to their digital counterparts. In fact, a commercial analog class-IV partial-response sequence detector for magnetic read channels has already been reported. Analog decoders offer the advantages of reduced power and size primarily due to the elimination of the A/D. The analog Viterbi decoder described here is less complex and more robust compared to other reported realizations. The decoder is based on a new derivation of the difference-metric algorithm which is developed from an analog implementation perspective. This has resulted in a decrease in hardware complexity thereby making an analog approach more attractive for today's demanding high-speed, low-power, and small-size applications, such as magnetic diskdrive storage systems. The decoder was fabricated in a 0.8-m BiCMOS process. It consists of two time-interleaved dicodes and the interleaving circuitry. The decoder was tested at up to 100 MS/s. However, si...

We describe the implementation of a hidden Markov model state decoding system, a component for a wordspotting speech recognition system. The key specification for this state decoder design is microwatt power dissipation; this requirement led to a continuoustime, analog circuit implementation. We describe the tradeoffs inherent in the choice of an analog design and explain the mapping of the discrete-time state decoding algorithm into the continuous domain. We characterize the operation of a 10-word (81 state) state decoder test chip. 1. INTRODUCTION Digital implementations of signal processing systems have numerous advantages over their analog counterparts, including accuracy, immunity from temperatureand supply-induced variations, and ease of design and test. These advantages make digital the default implementation choice in many application domains. In certain applications, however, a particular system requirement is much easier to achieve in an analog implementation. Power consumpt...

Motivated by previous comparison work, a configuration for partial response maximum likelihood detection using the Viterbi algorithm (PRML/VA) detectors with adaptive target polynomials is examined. In this configuration, a mean-quared error decision feedback equalization (MSE-DFE) is used to adapt both the forward equalizer and the target channel for the Viterbi detector. The performance of this adaptive PRML/VA is analyzed and compared with other detection techniques. The issue of convergence speed is also studied. Index Terms---Adaptive target polynomials, analytical performance comparison, partial response maximum likelihood detection. I. INTRODUCTION P ARTIAL response maximum likelihood detection using the Viterbi algorithm (PRML/VA) [9], decision feedback equalization (DFE) [10], [13], and fixed-delay tree search with decision feedback (FDTS/DF) [2] are the three sampling detection techniques most often considered for digital magnetic recording. In a previous paper, detailed p...

A 170-MHz analog finite impulse response (FIR) filter operating from a single 3.3-V supply is described. The design has been fabricated in the HP 1.2-m CMOS process and has an area of 2.35 mm by 1.97 mm including bonding pads. This 9tap filter dissipates 70 mW when operating at 170 MHz. The multipliers are implemented using multiplying digital-to-analog converters (MDAC's) with 6-b resolution. Index Terms---Analog FIR filter, circular buffer architecture, discrete-time, fixed pattern noise, low power CMOS circuits. I. INTRODUCTION M ANY applications require high-speed low-power equalizers with moderate resolution. Analog equalizers are almost ideally suited for these applications since they can typically provide the required performance with less power and area than their digital counterparts. As an example, modern magnetic storage channels, which usually use partial-response maximum-likelihood (PRML) detection, require a linear equalizer to shape the channel response [1]--[4]. Th...

A fully integrated analog timing recovery circuit for partial-response maximum-likelihood (PRML) detectors for digital magnetic storage is described. The circuit uses a decision -directed minimum mean-squared error (MMSE) algorithm and achieves phase acquisition within 100-bit periods at a maximum speed of 180 Mb/s. It dissipates 76 mW from a single 3.3-V supply and has an active die area of 1.8 mm 2 in a 1.2- m CMOS process. At 180 Mb/s, the rms clock jitter is 15 ps and peak-to-peak jitter is 97 ps. The test results demonstrate the feasibility of an analog CMOS implementation of decision-directed MMSE timing recovery for PRML detectors. Index Terms---Analog integrated circuits, digital magnetic recording, least mean square methods, partial reponse signaling, synchronization, timing jitter. I. INTRODUCTION I N THE early 1990's, most disk drives used continuous-time analog peak detection to recover stored data. In this type of read channel the detected peaks contain timing informat...

The objective of the proposed research is to realize a 10-Gb/sec serial data link over band-limited channels, such as backplanes, multi-mode fiber, and copper-based cables that were originally designed for data rates less than 1Gb/sec. This is achieved using electrical equalization implemented in an integrated circuit (IC). To successfully compensate for various band-limited channels at the targeted data rate with a single equalizer IC, a reconfigurable equalizer topology is proposed. In order to realize the proposed goal, various channels are characterized of their forward transmission frequency response. Based on the measured channel data, system simulations are performed to identify the required specifications for IC implementation. This provides information such as optimal number of taps, fractionally-spaced tap delay, and tap coefficients for the proposed IC. With the obtained system requirements, IC building blocks are designed and fabricated in a 0.18- and #956;m CMOS technology. The fully-integrated reconfigurable CMOS equalizer provides a single-chip solution for compensating various band-limited channels. This enables 10-Gb/sec serial data transmission achieving signal integrity beyond their designed specifications.

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