Introduction: Sources of Variation Variation is the deviation from intended or designed values for a structure or circuit parameter of concern. The electrical performance of microprocessors or other integrated circuits are impacted bytwo sources of variation. First, environmental factors are those which arise during the operation of a circuit, and include variations in power supply, switching activity, and temperature of the chip or across the chip. These variations depend primarily on architectural and operating decisions such as power grid design and component placement. Time-varying (temporal) variation in these environment parameters can be a significant design concern. Circuit robustness to noise, cross-talk, and time- and switching-related aging or reliability factors must be considered carefully during circuit design. In this chapter, we will focus on a second category of variation sources. Physical factors during manufacture result in struct

Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, sophisticated tampering methods have been devised to extract secret keys stored in digital integrated circuits (ICs) from conditional access systems such as smartcards and ATMs. Arbiter-based Physical Unclonable Functions (PUFs) is proposed to exploit the statistical delay variation of wires and transistors across ICs in a manufacturing process to build unextractable secret keys. We fabricated arbiter-based PUFs in custom silicon and investigated the identification capability, reliability, and security of this scheme. Experimental results and theoretical studies show that a sufficient amount of inter-chip variation exists to enable each IC to be identified reliably and securely over a practical range of environmental variations such as temperature and power supply voltage. We show that arbiter-based PUFs are realizable and well-suited to build, for example, key-cards that need to be resistant to physical tampering attacks. 1

A statistical performance simulation (SPS) methodology for VLSI circuits is presented. Traditional methods of worst-case corner analysis lack accuracy and Monte-Carlo simulations cannot be applied to VLSI circuits because of their complexity. SPS methodology is accurate because no statistical information about the device parameter variation is lost. It achieves efficiency by analyzing the smaller circuit blocks and generating the performance distribution for the entire circuit. Circuit evaluation at any specified performance level is possible. 1 INTRODUCTION Deep sub-micron technologies have made the problem of statistical modeling of the device and circuit behavior more critical. Shrinking dimensions make device characteristics more sensitive to stochastic process variation. Thus the relative spread of device and circuit behaviors is broadened. Combined with the continuing reduction of the design cycle, this creates an urgent need for methodologies that can accurately model and pred...

A new statistical parameter extraction methodology which translates actual process variations into SPICE model parameter variations is presented. This methodology uses E-T data to extract SPICE model parameters and guarantees that its extraction results match measured variations. We have applied this methodology to an industrial 0.5μm process. Excellent, overall I-V curve fit for multiple device geometries is achieved. A compact statistical circuit design technology that improves upon the typical/worst/best case methodology is also presented. I.

This paper presents a computationally efficient means for estimating parametric timing yield and guiding robust design-for-quality in the presence of manufacturing and operating environment variations. Computational efficiency is achieved by basing the proposed methodology on a post-processing step applied to the report generated as a by-product of static timing analysis. Efficiency is also ensured by exploiting the fact that for small processing/environment variations, a linear model is adequate for capturing the resulting delay change. Meaningful design guidance is achieved by analyzing the timing-related influence of variations on a path-by-path basis, allowing designers perform a quality-oriented design pass focused on key paths. A coherent strategy is

Towards predictable deep-submicron manufacturing

and test pattern ordering for scan designs, ” in Proc. Int. Test Conf.,