A compiler for multi-threaded object-oriented programs needs information about the sharing of objects for a variety of reasons: to implement optimizations, to issue warnings, to add instrumentation to detect access violations that occur at runtime. An Object Use Graph (OUG) statically captures accesses from different threads to objects. An OUG extends the Heap Shape Graph (HSG), which is a compile-time abstraction for runtime objects (nodes) and their reference relations (edges). An OUG specifies for a specific node in the HSG a partial order of events relevant to the corresponding runtime object(s). Relevant events include read and write access, object escape, thread start and join. OUGs have been implemented...

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Abstract. We present a class of relaxed memory models, defined in Coq, parameterised by the chosen permitted local reorderings of reads and writes, and the visibility of inter- and intra-processor communications through memory (e.g. store atomicity relaxation). We prove results on the required behaviour and placement of memory fences to restore a given model (such as Sequential Consistency) from a weaker one. Based on this class of models we develop a tool, diy, that systematically and automatically generates and runs litmus tests to determine properties of processor implementations. We detail the results of our experiments on Power and the model we base on them. This work identified a rare implementation error in Power 5 memory barriers (for which IBM is providing a workaround); our results also suggest that Power 6 does not suffer from this problem. 1

Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by executing a memory barrier instruction, ensuring that recent writes have been ordered with respect to other processors in the system. We show that this model leads to superfluous memory barriers in programs with acquire-release style synchronization, and present a combined hardware/software synchronization mechanism called conditional memory ordering (CMO) that reduces memory ordering overhead. CMO is demonstrated on a lock algorithm that identifies those dynamic lock/unlock operations for which memory ordering is unnecessary, and speculatively omits the associated memory ordering instructions. When ordering is required, this algorithm relies on a hardware mechanism for initiating a memory ordering operation on another processor. Based on evaluation using a software-only CMO prototype, we show that CMO avoids memory ordering operations for the vast majority of dynamic acquire and release operations across a set of multithreaded Java workloads, leading to significant speedups for many. However, performance improvements in the software prototype are hindered by the high cost of remote memory ordering. Using empirical data, we construct an analytical model demonstrating the benefits of a combined hardware-software implementation. 1

Because data races represent a hard-to-manage class of errors in concurrent programs, numerous approaches to detect them have been proposed and evaluated. We specifically consider asymmetric races, a subclass of all race conditions, where a programmer’s thread correctly acquires and releases a lock for a given variable, while another thread causes a race by improperly accessing this variable. We introduce ToleRace, a runtime system that allows programs to either tolerate or detect asymmetric races based on local replication of shared state. ToleRace provides an approximation of atomicity in critical sections by creating local copies of shared variables when a critical section is entered and propagating the appropriate copy when the critical section is exited. We characterize the possible interleavings that can cause races and precisely describe the effect of ToleRace in each case. We study the theoretical aspects of an oracle that knows exactly what type of interleaving has occurred. Then, we present a software implementation of ToleRace on top of a dynamic instrumentation tool. We evaluate our implementation on multithreaded applications from the SPLASH2 and PARSEC suites and show that its overhead is acceptable, i.e., a factor of two on average.

This dissertation develops and exploits a formalism for specifying memory consistency models. This formalism lays down the foundations for describing memory consistency models at various levels, and develops techniques to prove the equivalence between mod-els defined at different levels. Two levels, called non-operational and operational, are ad-dressed in this dissertation. The non-operational level describes these models in terms of program instructions or procedures, while the operational level describes them in terms of implementation events. Formal techniques are developed to prove the equivalence of rigorous specifications at both levels. This formalism is then exploited to define the memory consistency models of two state-of-the-art multiprocess systems: the SPARC version 8 architecture and the Java Virtual Machine. These models are defined at both operational and non-operational levels. These operational and non-operational descriptions are proved equivalent. The SPARC models provide “reasonably” weak memory consistency models that are capable of avoiding the use of explicit synchronization primitives for certain problems. However, Java provides

In machines with weak memory consistency models, the ordering constraints on memory accesses are few. In order to properly program these machines, certain powerful explicit synchronization instructions are additionally provided by their architecture. We show that although a solution to the critical section problem (also referred to as the mutual exclusion problem) is impossible without such powerful synchronization, certain versions of the producer/consumer problem can be solved even in the weakest systems without the need for any such powerful instructions. These instructions are expensive, and avoiding their use is desirable for better performance. 1 Introduction The problem of process coordination has been extensively addressed in the context of sequential consistency. However, modern multiprocessors present a large variety of memory models that are anything but sequentially consistent. Relaxed memory consistency models increase the challenge of solving various coordination proble...

We address the problem, proposed by Gerth, of verifying that a simplified version of the lazy caching algorithm of Afek, Brown, and Merritt is sequentially consistent. We specify the algorithm and sequential consistency in TLA+, a formal specification language based on TLA (the Temporal Logic of Actions). We then describe how to construct and check a formal TLA correctness proof.

Abstract. Shared memory multiprocessors typically expose subtle, poorly understood and poorly specified relaxed-memory semantics to programmers. To understand them, and to develop formal models to use in program verification, we find it essential to take an empirical approach, testing what results parallel programs can actually produce when executed on the hardware. We describe a key ingredient of our approach, our litmus tool, which takes small ‘litmus test ’ programs and runs them for many iterations to find interesting behaviour. It embodies various techniques for making such interesting behaviour appear more frequently. 1

utual exclusion: memory operations act as if all those in one critical section were performed either before or after all those in another. Virtual mutual exclusion says nothing about when the operations are really performed. As an example, consider the following basic mutual exclusion protocol that is used by several standard algorithms. Processor A: a : = 1; if b = 0 then critical section; a : = 0 f i Processor B : b : = 1; if a = 0 then critical section; b : = 0 f i 1 Suppose neither of the critical sections accesses a, b, or any variable accessed by the other. A multiprocessor could execute processor A's assignment a := 1, its if test, and its assignment a := 0, and then