Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the technology feature size rapidly decreases towards below 0.1 micron. Then, we present commonly used interconnect models and a set of interconnect design and optimization techniques for improving interconnect performance and reliability. Finally, we present comparisons of different optimization techniques in terms of their efficiency and optimization results, and show the impact of these optimization techniques on interconnect performance in each technology generation from the 0.35µm to 0.07µm projected in the National Technology Roadmap for Semiconductors.

We describe a novel iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. Our new approach is considerably faster than previous methods for computing effective capacitance, with little or no loss of accuracy. Thus, the approach is suitable within the analysis loop for performance-driven iterative layout optimization. After reviewing previous gate load models and effective capacitance approximations, we separately derive our method for the cases of step and ramp waveform at the gate output, and note ongoing extensions for the case of complex gates (e.g., channel-connected components). Experimental results using the new effective capacitance approach show that our resulting delay estimates are quite accurate -- within 15% of HSPICE-computed delays on data corresponding to an 0.25µm microprocessor design. 1 Introduction With interconnect delays dominating overall path delays for deep-submicron integrated circuits, heuristics for...

We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach makes it suitable for the analysis loop within performance-driven iterative layout optimization. We present an iterationless approach for computing the effective capacitance of an interconnect load at a gate output when the slew time is non-zero (i.e., a ramp). We then extend this effective capacitance algorithm to complex gates, i.e., channel-connected components. Preliminary experimental results using the new effective capacitance approach show that the resulting delay estimates are quite accurate -- within 15% of HSPICE-computed delays on data taken from a recent microprocessor design in 0.25µm CMOS technology. The improved driver model reduces the cell delay calculation errors to below 10%; this indicates that accurate modeling of effective capacitance is no longer the dominant source of errors in cell delay ...

This paper presents an overview of recent advances on modeling and layout optimization of devices and interconnects for high-performance VLSI circuit design under the deep submicron technology. First, we review a number of interconnect and driver/gate delay models, which are most useful to guide the layout optimization. Then, we summarize the available performance optimization techniques for VLSI device and interconnect layout, including driver and transistor sizing, transistor ordering, interconnecttopology optimization, optimal wire sizing, optimal buffer placement, and simultaneous topology construction, buffer insertion, buffer and wire sizing. The efficiency and impact of these techniques will be discussed in the tutorial.