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A CMOS fourquadrant analog current multiplier
 Proc. IEEE Int. Symp. Circ. and Systems
, 1991
"... Ab In this paper a CMOS feurqnadrant d o g enrrent mpltiplkr b dcrerikd. 'Ik drcllit b b.sed om tbe scpu+lnw eLrvtaWicduMOSb.nsisbrandb~vcbtrmplrture andprocm nrttioor.~thedn!nitisbtivetothe body effect eo It b wt mecesmqb place tnnsbtwa i.individd web. TLC mdtijdk has a3dB budrridtb (Se MA ..."
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Ab In this paper a CMOS feurqnadrant d o g enrrent mpltiplkr b dcrerikd. 'Ik drcllit b b.sed om tbe scpu+lnw eLrvtaWicduMOSb.nsisbrandb~vcbtrmplrture andprocm nrttioor.~thedn!nitisbtivetothe body effect eo It b wt mecesmqb place tnnsbtwa i.individd web. TLC mdtijdk has a3dB budrridtb (Se MAZ uitb lOum ksbtem) and an approximately camstant hput impedance Tbe circa & was a om 8 CMOS sunkustom anay. Measnremcnts have shown that the nonlinearity is h than 1 % at the maximum input cwremt range and h tSllllO29bwben the input mnge is restricted to SO%dthcruilm. I. INTRODUCIION The quarter square principle is a well known technique to realize a multiplier. Various multipliers based on this principle have been reported [l], [2], [3]. For signals in the form of currents the principle can be written as: So, in order to multiply the input currents I, and I, we can square both the sum and the difference of these currents and then subtract the results from eachother. In the next section a suitable current squarer will be described. In section III, two of these squaring circuits will be combined to realize the fourquadrant current multiplier. Section IV describes secondorder effects. The results of simulations and measurements on both the squaring circuit and the complete multiplier are presented in section V. n. THE CURRENTSQUARING CIRCUIT A schematic diagram of the squaring circuit is shown in fig. 1. All transistors are equal and operate in the saturation region. Using a simple squarelaw model, the drain current of an MOS transistor in the saturation region can be written as: MOS translinear loop [4]. From Kirchhoff s voltage law, it follows that: V,l+ v,2 = v,3+ v,4 (4) (5) If the bodyeffect is represented as a change in threshold voltage as a function of the sourcebulk voltage it is easily seen that the effect is equal for transistors Mi and M.I and transistors M2 and Ms Therefore, +v;l will be equal to 6 4 and Vn will be equal to 6 3 and the threshold voltages can be dropped from eqn. (5). If we assume equal transistors and neglect the slight influence of the bodyeffect on ki, k2, k3 and k4 these factors can also be dropped. The result is: G+G=G+dG (6) This relation is temperature and process independent.
An analog VLSI chip for estimating the focus of expansion
 In 1997 ISSCC Digest of Technical Papers
, 1996
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A Parallel Structure for CMOS FourQuadrant Analog Multipliers and its Application to a 2 GHz RF Downconversion Mixer
 IEEE J. SolidState Circuits
, 1998
"... Abstract—A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog ..."
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Abstract—A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog multiplier is designed and fabricated by 0.8m Nwell doublepolydoublemetal CMOS technology. Experimental results have shown that, under a single 1.2V supply voltage, the circuit has 0.89 % linearity error and 1.1 % total harmonic distortion under the maximumscale input 500mV PP at both multiplier inputs. The 3dB bandwidth is 2.2 MHz and the dc current is 2.3 mA. By using the proposed multiplier as a mixercore and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5m singlepolydoublemetal Nwell CMOS technology. The experimental results have shown that, under 3V supply voltage and 2dBm LO power, the mixer has 1dB conversion gain, 2.2GHz input bandwidth, 180MHz output bandwidth, and 22dB noise figure. Under the LO frequency 1.9 GHz and the total dc current 21 mA, the thirdorder input intercept point is +7.5 dBm and the input 1dB compression point is 9 dBm. Index Terms—Analog multiplier, low voltage, RF mixer, wireless communication. I.
OTABased High Frequency CMOS Multiplier and Squaring Circuit
"... Abstract A gigahertz analog multiplier based on OTA and squaring is proposed. The multiplier has gigahertz frequency response is suitable to use in communication system. The circuit is based on 0.18 µm CMOS technology simulated using PSPICE level 7. This technique provides; wide dynamic range, GHz ..."
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Abstract A gigahertz analog multiplier based on OTA and squaring is proposed. The multiplier has gigahertz frequency response is suitable to use in communication system. The circuit is based on 0.18 µm CMOS technology simulated using PSPICE level 7. This technique provides; wide dynamic range, GHzbandwidth response and low power consumption. The proposed circuit has been simulated with PSPICE and achieved3dB bandwidth of 3.96GHz. The total power dissipation is 0.588mW with ±1V power supply voltages.. I.
A NEW LOW DISTORTION ANALOG MULTIPLIER
"... A new method has been proposed to reduce the mobility degradation effect on squarelaw characteristic of the MOS transistor. This method has been applied to an analog multiplier to form a new low distortion multiplier circuit. This analog multiplier operates with ± 5V power supply. The operating ran ..."
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A new method has been proposed to reduce the mobility degradation effect on squarelaw characteristic of the MOS transistor. This method has been applied to an analog multiplier to form a new low distortion multiplier circuit. This analog multiplier operates with ± 5V power supply. The operating range for each input is ± 3V. In this operating range the nonlinearity for Vx is 0.6 % and for Vy is 0.5%. The 3dB bandwidth is specified for Vx as 33MHz and for Vy as 34MHz, respectively. I.
PERFORM SIGNALPROCESSING USING Approved by: FLOATINGGATE MOS DEVICE FOR PORTABLE APPLICATIONS
, 2004
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Linear Phase Filter With OnChip Automatic Tuning System
"... Abstract—A full CMOS seventhorder linear phase filter based on – biquads with a 3dB frequency of 200 MHz is realized in 0.35 m CMOS process. The linear operational transconductance amplifier is based on complementary differential pairs in order to achieve both lowdistortion figures and highfr ..."
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Abstract—A full CMOS seventhorder linear phase filter based on – biquads with a 3dB frequency of 200 MHz is realized in 0.35 m CMOS process. The linear operational transconductance amplifier is based on complementary differential pairs in order to achieve both lowdistortion figures and highfrequency operation. The commonmode feedback (CMFB) employed takes advantage of the filter architecture; incorporating the load capacitors into the CMFB loop improves further its phase margin. A very simple automatic tuning system corrects the filter deviations due to process parameter tolerances and temperature variations. The group delay ripple is less than 5 % for frequencies up to 300 MHz, while the power consumption is 60 mW. The thirdharmonic distortion is less than 44 dB for input signals up to 500 mV pp. The filter active area is only 900 200 m2. The supply voltages used are 1.5 V. Index Terms—Automatic tuning systems, commonmode feedback circuits (CMFB), continuoustime filters, linear operational transconductance amplifiers. I.
±0.5V ~ ±1.5V VHF CMOS LV/LP FourQuadrant Analog Multiplier in Modified BridgedTriode Scheme
"... A new LV/LP CMOS fourquadrant analog multiplier designed in a modified bridgedtriode scheme (MBTS) is presented. It brings in the benefits in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The fabricated chip in TSMC 0.35µm nwell SPQM CMOS technolog ..."
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A new LV/LP CMOS fourquadrant analog multiplier designed in a modified bridgedtriode scheme (MBTS) is presented. It brings in the benefits in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The fabricated chip in TSMC 0.35µm nwell SPQM CMOS technology has a nonlinearity error less than 0.8 % over ±0.5V input range under a nominal supply voltage of ±1.5V, and consumes the total power dissipation of 2.7 mW only. Categories & Subject Descriptors