Results 1 
5 of
5
A CMOS fourquadrant analog current multiplier
 Proc. IEEE Int. Symp. Circ. and Systems
, 1991
"... Ab In this paper a CMOS feurqnadrant d o g enrrent mpltiplkr b dcrerikd. 'Ik drcllit b b.sed om tbe scpu+lnw eLrvtaWicduMOSb.nsisbrandb~vcbtrmplrture andprocm nrttioor.~thedn!nitisbtivetothe body effect eo It b wt mecesmqb place tnnsbtwa i.individd web. TLC mdtijdk has a3dB budrridtb (Se MAZ uit ..."
Abstract

Cited by 7 (0 self)
 Add to MetaCart
Ab In this paper a CMOS feurqnadrant d o g enrrent mpltiplkr b dcrerikd. 'Ik drcllit b b.sed om tbe scpu+lnw eLrvtaWicduMOSb.nsisbrandb~vcbtrmplrture andprocm nrttioor.~thedn!nitisbtivetothe body effect eo It b wt mecesmqb place tnnsbtwa i.individd web. TLC mdtijdk has a3dB budrridtb (Se MAZ uitb lOum ksbtem) and an approximately camstant hput impedance Tbe circa & was a om 8 CMOS sunkustom anay. Measnremcnts have shown that the nonlinearity is h than 1 % at the maximum input cwremt range and h tSllllO29bwben the input mnge is restricted to SO%dthcruilm. I. INTRODUCIION The quarter square principle is a well known technique to realize a multiplier. Various multipliers based on this principle have been reported [l], [2], [3]. For signals in the form of currents the principle can be written as: So, in order to multiply the input currents I, and I, we can square both the sum and the difference of these currents and then subtract the results from eachother. In the next section a suitable current squarer will be described. In section III, two of these squaring circuits will be combined to realize the fourquadrant current multiplier. Section IV describes secondorder effects. The results of simulations and measurements on both the squaring circuit and the complete multiplier are presented in section V. n. THE CURRENTSQUARING CIRCUIT A schematic diagram of the squaring circuit is shown in fig. 1. All transistors are equal and operate in the saturation region. Using a simple squarelaw model, the drain current of an MOS transistor in the saturation region can be written as: MOS translinear loop [4]. From Kirchhoff s voltage law, it follows that: V,l+ v,2 = v,3+ v,4 (4) (5) If the bodyeffect is represented as a change in threshold voltage as a function of the sourcebulk voltage it is easily seen that the effect is equal for transistors Mi and M.I and transistors M2 and Ms Therefore, +v;l will be equal to 6 4 and Vn will be equal to 6 3 and the threshold voltages can be dropped from eqn. (5). If we assume equal transistors and neglect the slight influence of the bodyeffect on ki, k2, k3 and k4 these factors can also be dropped. The result is: G+G=G+dG (6) This relation is temperature and process independent.
An Analog VLSI Chip for Estimating the Focus of Expansion
 In 1997 ISSCC Digest of Technical Papers
, 1996
"... For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a realtime analog vlsi chip which estimates the focus of expansion (foe) from measured timevarying ima ..."
Abstract

Cited by 6 (1 self)
 Add to MetaCart
For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a realtime analog vlsi chip which estimates the focus of expansion (foe) from measured timevarying images. Our approach assumes a camera moving through a fixed world with translational velocity; the foe is the projection of the translation vector onto the image plane. This location is the point towards which the camera is moving, and other points appear to be expanding outward from. By way of the camera imaging parameters, the location of the foe gives the direction of 3D translation. The algorithm we use for estimating the foe minimizes the sum of squares of the differences at every pixel between the observed time variation of brightness and the predicted variation given the assumed position of the foe. This minimization is not straightforward, because the relationship between the brightn...
A Parallel Structure for CMOS FourQuadrant Analog Multipliers and Its Application to a 2GHz RF Downconversion Mixer
 IEEE Journal of solid state circuits
, 1998
"... A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog multiplier ..."
Abstract

Cited by 2 (0 self)
 Add to MetaCart
A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog multiplier is designed and fabricated by 0.8m Nwell doublepoly doublemetal CMOS technology. Experimental results have shown that, under a single 1.2V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximumscale input 500mVPP at both multiplier inputs. The 03dB bandwidth is 2.2 MHz and the dc current is 2.3 mA. By using the proposed multiplier as a mixercore and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5m singlepolydoublemetal Nwell CMOS technology. The experimental results have shown that, under 3V supply voltage and 2dBm LO power, the mixer has 01dB conversion gain, 2....
OTABased High Frequency CMOS Multiplier and Squaring Circuit
"... Abstract A gigahertz analog multiplier based on OTA and squaring is proposed. The multiplier has gigahertz frequency response is suitable to use in communication system. The circuit is based on 0.18 µm CMOS technology simulated using PSPICE level 7. This technique provides; wide dynamic range, GHz ..."
Abstract

Cited by 1 (0 self)
 Add to MetaCart
Abstract A gigahertz analog multiplier based on OTA and squaring is proposed. The multiplier has gigahertz frequency response is suitable to use in communication system. The circuit is based on 0.18 µm CMOS technology simulated using PSPICE level 7. This technique provides; wide dynamic range, GHzbandwidth response and low power consumption. The proposed circuit has been simulated with PSPICE and achieved3dB bandwidth of 3.96GHz. The total power dissipation is 0.588mW with ±1V power supply voltages.. I.
doi:10.3906/elk1001377
"... A novel fourquadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement t ..."
Abstract
 Add to MetaCart
A novel fourquadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only six FGMOS transistors. The main features of this remarkably simple multiplier circuit configuration are the large input signal range equal to 100 % of the supply voltage, nonlinearity of 0.0081%, bandwidth of 1.4–1.5 Ghz and THD of maximum 2.67 % (while the inputs are at their maximum values). Key Words: FGMOS, four quadrant analog multiplier, railtorail, differential amplifier 1.