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An Analog VLSI Chip for Estimating the Focus of Expansion
 In 1997 ISSCC Digest of Technical Papers
, 1996
"... For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a realtime analog vlsi chip which estimates the focus of expansion (foe) from measured timevarying ima ..."
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Cited by 6 (1 self)
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For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a realtime analog vlsi chip which estimates the focus of expansion (foe) from measured timevarying images. Our approach assumes a camera moving through a fixed world with translational velocity; the foe is the projection of the translation vector onto the image plane. This location is the point towards which the camera is moving, and other points appear to be expanding outward from. By way of the camera imaging parameters, the location of the foe gives the direction of 3D translation. The algorithm we use for estimating the foe minimizes the sum of squares of the differences at every pixel between the observed time variation of brightness and the predicted variation given the assumed position of the foe. This minimization is not straightforward, because the relationship between the brightn...
A Parallel Structure for CMOS FourQuadrant Analog Multipliers and Its Application to a 2GHz RF Downconversion Mixer
 IEEE Journal of solid state circuits
, 1998
"... A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog multiplier ..."
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Cited by 2 (0 self)
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A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog multiplier is designed and fabricated by 0.8m Nwell doublepoly doublemetal CMOS technology. Experimental results have shown that, under a single 1.2V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximumscale input 500mVPP at both multiplier inputs. The 03dB bandwidth is 2.2 MHz and the dc current is 2.3 mA. By using the proposed multiplier as a mixercore and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5m singlepolydoublemetal Nwell CMOS technology. The experimental results have shown that, under 3V supply voltage and 2dBm LO power, the mixer has 01dB conversion gain, 2....
A Currentmode Multiplier/Divider Employing Only Single DualOutput Current Controlled CDTA
"... This paper reviews a circuit, which is analog multiplier/divider using merely single DualOutput Current Controlled Current Differencing Transconductance Amplifiers (DOCCCDTA). The proposed circuit can function as a fourquadrant multiplier and twoquadrant divider without changing a circuit topolo ..."
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This paper reviews a circuit, which is analog multiplier/divider using merely single DualOutput Current Controlled Current Differencing Transconductance Amplifiers (DOCCCDTA). The proposed circuit can function as a fourquadrant multiplier and twoquadrant divider without changing a circuit topology. A constant value of multiplication and division can be controlled via an input bias current. Without any external passive element requirements and using only single DOCCCDTA, the proposed circuit is suitable to fabricate in IC. The circuit performances are depicted trough PSPICE simulations, they show good agreement to theoretical analysis.
OTABased High Frequency CMOS Multiplier and Squaring Circuit
"... Abstract A gigahertz analog multiplier based on OTA and squaring is proposed. The multiplier has gigahertz frequency response is suitable to use in communication system. The circuit is based on 0.18 µm CMOS technology simulated using PSPICE level 7. This technique provides; wide dynamic range, GHz ..."
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Abstract A gigahertz analog multiplier based on OTA and squaring is proposed. The multiplier has gigahertz frequency response is suitable to use in communication system. The circuit is based on 0.18 µm CMOS technology simulated using PSPICE level 7. This technique provides; wide dynamic range, GHzbandwidth response and low power consumption. The proposed circuit has been simulated with PSPICE and achieved3dB bandwidth of 3.96GHz. The total power dissipation is 0.588mW with ±1V power supply voltages.. I.
Analog Signal Processing Circuits Using Floating Gate MOS Transistors
"... Abstract – Low voltage nonlinear computational circuits useful for analog VLSI signal processing applications based on floating gate MOS transistors (FGMOSFETs) are presented. The FGMOS transistors operate in the saturation region. The variable equivalent threshold voltage (VT) of the FGMOS transis ..."
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Abstract – Low voltage nonlinear computational circuits useful for analog VLSI signal processing applications based on floating gate MOS transistors (FGMOSFETs) are presented. The FGMOS transistors operate in the saturation region. The variable equivalent threshold voltage (VT) of the FGMOS transistor is exploited in such a way to transform it to a simple MOSFET of zero VT. A bias circuit using a conventional VT extractor circuit makes the transformation. The transistor behaves as a simple squaring element in this case. A fourquadrant multiplier and a Euclidean norm calculator circuit are presented as applications. The most important advantages of the fourquadrant multiplier are railtorail dynamic input range, low distortion and very good linearity. The main advantages of the Euclidean norm calculator circuit are unipolar supply voltage, linear expansion requiring only one FGMOS per additional input and very good linearity. SPICE simulation results verify the accuracy of the circuits. Index Terms – Floating gate MOSFETs, VT cancellation circuit, fourquadrant multiplier, Euclidean norm calculator circuit, analog VLSI signal processing. I.
doi:10.3906/elk1001377
"... A novel fourquadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement t ..."
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A novel fourquadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only six FGMOS transistors. The main features of this remarkably simple multiplier circuit configuration are the large input signal range equal to 100 % of the supply voltage, nonlinearity of 0.0081%, bandwidth of 1.4–1.5 Ghz and THD of maximum 2.67 % (while the inputs are at their maximum values). Key Words: FGMOS, four quadrant analog multiplier, railtorail, differential amplifier 1.
Hippocampal Formation v TABLE OF CONTENTS
, 1993
"... Iwould especially like to thank Steve Levitan and Robert Sclabassi for their guidance, support and patience throughout the development of this project; Steve Frezza and YeeWing Hsieh for reading my thesis and correcting the grammatical mistakes. Finally, special thanks to my parents, Kwan Yeung Chi ..."
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Iwould especially like to thank Steve Levitan and Robert Sclabassi for their guidance, support and patience throughout the development of this project; Steve Frezza and YeeWing Hsieh for reading my thesis and correcting the grammatical mistakes. Finally, special thanks to my parents, Kwan Yeung Chiu and Kwan Chan Yin Fong; my sisters, Grace, Claudine and Josephine, for their support.