For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a real-time analog vlsi chip which estimates the focus of expansion (foe) from measured time-varying images. Our approach assumes a camera moving through a fixed world with translational velocity; the foe is the projection of the translation vector onto the image plane. This location is the point towards which the camera is moving, and other points appear to be expanding outward from. By way of the camera imaging parameters, the location of the foe gives the direction of 3-D translation. The algorithm we use for estimating the foe minimizes the sum of squares of the differences at every pixel between the observed time variation of brightness and the predicted variation given the assumed position of the foe. This minimization is not straightforward, because the relationship between the brightn...

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8-m N-well doublepoly -double-metal CMOS technology. Experimental results have shown that, under a single 1.2-V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500-mVP-P at both multiplier inputs. The 03-dB bandwidth is 2.2 MHz and the dc current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5-m single-poly-doublemetal N-well CMOS technology. The experimental results have shown that, under 3-V supply voltage and 2-dBm LO power, the mixer has 01-dB conversion gain, 2....

Abstract – Low voltage non-linear computational circuits useful for analog VLSI signal processing applications based on floating gate MOS transistors (FGMOSFETs) are presented. The FGMOS transistors operate in the saturation region. The variable equivalent threshold voltage (VT) of the FGMOS transistor is exploited in such a way to transform it to a simple MOSFET of zero VT. A bias circuit using a conventional VT extractor circuit makes the transformation. The transistor behaves as a simple squaring element in this case. A four-quadrant multiplier and a Euclidean norm calculator circuit are presented as applications. The most important advantages of the four-quadrant multiplier are rail-to-rail dynamic input range, low distortion and very good linearity. The main advantages of the Euclidean norm calculator circuit are unipolar supply voltage, linear expansion requiring only one FGMOS per additional input and very good linearity. SPICE simulation results verify the accuracy of the circuits. Index Terms – Floating gate MOSFETs, VT cancellation circuit, four-quadrant multiplier, Euclidean norm calculator circuit, analog VLSI signal processing. I.

A novel four-quadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only six FGMOS transistors. The main features of this remarkably simple multiplier circuit configuration are the large input signal range equal to 100 % of the supply voltage, nonlinearity of 0.0081%, bandwidth of 1.4–1.5 Ghz and THD of maximum 2.67 % (while the inputs are at their maximum values). Key Words: FGMOS, four quadrant analog multiplier, rail-to-rail, differential amplifier 1.

Iwould especially like to thank Steve Levitan and Robert Sclabassi for their guidance, support and patience throughout the development of this project; Steve Frezza and Yee-Wing Hsieh for reading my thesis and correcting the grammatical mistakes. Finally, special thanks to my parents, Kwan Yeung Chiu and Kwan Chan Yin Fong; my sisters, Grace, Claudine and Josephine, for their support.