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An Analog VLSI Chip for Estimating the Focus of Expansion
 In 1997 ISSCC Digest of Technical Papers
, 1996
"... For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a realtime analog vlsi chip which estimates the focus of expansion (foe) from measured timevarying ima ..."
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Cited by 6 (1 self)
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For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a realtime analog vlsi chip which estimates the focus of expansion (foe) from measured timevarying images. Our approach assumes a camera moving through a fixed world with translational velocity; the foe is the projection of the translation vector onto the image plane. This location is the point towards which the camera is moving, and other points appear to be expanding outward from. By way of the camera imaging parameters, the location of the foe gives the direction of 3D translation. The algorithm we use for estimating the foe minimizes the sum of squares of the differences at every pixel between the observed time variation of brightness and the predicted variation given the assumed position of the foe. This minimization is not straightforward, because the relationship between the brightn...
Accurate and Precise Computation using Analog VLSI, with Applications to Computer Graphics and Neural Networks
, 1993
"... This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI ..."
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Cited by 3 (1 self)
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This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multidimensional gradient estimation for a grad...
A Parallel Structure for CMOS FourQuadrant Analog Multipliers and Its Application to a 2GHz RF Downconversion Mixer
 IEEE Journal of solid state circuits
, 1998
"... A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog multiplier ..."
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Cited by 2 (0 self)
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A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog multiplier is designed and fabricated by 0.8m Nwell doublepoly doublemetal CMOS technology. Experimental results have shown that, under a single 1.2V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximumscale input 500mVPP at both multiplier inputs. The 03dB bandwidth is 2.2 MHz and the dc current is 2.3 mA. By using the proposed multiplier as a mixercore and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5m singlepolydoublemetal Nwell CMOS technology. The experimental results have shown that, under 3V supply voltage and 2dBm LO power, the mixer has 01dB conversion gain, 2....
doi:10.3906/elk1001377
"... A novel fourquadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement t ..."
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A novel fourquadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only six FGMOS transistors. The main features of this remarkably simple multiplier circuit configuration are the large input signal range equal to 100 % of the supply voltage, nonlinearity of 0.0081%, bandwidth of 1.4–1.5 Ghz and THD of maximum 2.67 % (while the inputs are at their maximum values). Key Words: FGMOS, four quadrant analog multiplier, railtorail, differential amplifier 1.