Results 1  10
of
12
Matching properties of MOS transistors
 IEEE J. SolidState Circuits
, 1989
"... AbstractThe matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for longdistance matching and rotation of devices. Matching parameters of several ..."
Abstract

Cited by 208 (1 self)
 Add to MetaCart
AbstractThe matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for longdistance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. 1.
A Capacitive ThresholdLogic Gate
, 1996
"... A dense and fast thresholdlogic gate with a very high fanin capacity is described. The gate performs sumofproduct and thresholding operations in an architecture comprising a polytopoly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This i ..."
Abstract

Cited by 26 (2 self)
 Add to MetaCart
A dense and fast thresholdlogic gate with a very high fanin capacity is described. The gate performs sumofproduct and thresholding operations in an architecture comprising a polytopoly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fanin 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described. I. INTRODUCTION T HRESHOLD logic (TL) originally emerged ...
A threeaxis micromachined accelerometer with a CMOS positionsense interface and digital offsettrim electronics
 IEEE Journal of SolidState Circuits
, 1999
"... Abstract — This paper describes a threeaxis accelerometer implemented in a surfacemicromachining technology with integrated CMOS. The accelerometer measures changes in a capacitive halfbridge to detect deflections of a proof mass, which result from acceleration input. The halfbridge is connected ..."
Abstract

Cited by 19 (3 self)
 Add to MetaCart
Abstract — This paper describes a threeaxis accelerometer implemented in a surfacemicromachining technology with integrated CMOS. The accelerometer measures changes in a capacitive halfbridge to detect deflections of a proof mass, which result from acceleration input. The halfbridge is connected to a fully differential positionsense interface, the output of which is used for onebit force feedback. By enclosing the proof mass in a onebit feedback loop, simultaneous force balancing and analogtodigital conversion are achieved. Onchip digital offsettrim electronics enable compensation of random offset in the electronic interface. Analytical performance calculations are shown to accurately model device behavior. The fabricated singlechip accelerometer measures 4 2 4mm P, draws 27 mA from a 5V supply, and has a dynamic range of 84, 81, and 70 dB along the �, �, and �axes, respectively. Index Terms—Accelerometer, calibration, force balance, microelectromechanical systems (MEMS), sensor, sigma–delta.
Transistor matching in analog CMOS applications
 IEEE International Electron Devices Meeting
, 1998
"... This paper gives an overview of MOSFET mismatch effects that form a performance/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit deof t ..."
Abstract

Cited by 11 (0 self)
 Add to MetaCart
This paper gives an overview of MOSFET mismatch effects that form a performance/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit deof these parallel paths (e.g. in multiplexers, comparators, input stages etc.) is important. Figure 8 will give an example of how transistor matching influences clock delay differences in clock trees. Hence, unequal paths lead to performance or yield loss in analog circuits or reduce robustness in digital circuits. Threshold matching sign is discussed. Mismatch effects gain importance The difference AVT between the threshold voltages as critical dimensions and CMOS power supply volt of a pair of MOS transistors (mismatch) is wuaily ages decrease. described[2], [3], [4],[5], [6], [7] by its standard deviation:
DFT for Digital Detection of Analog Parametric Faults in SC Filters
, 2000
"... Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is use ..."
Abstract

Cited by 4 (0 self)
 Add to MetaCart
Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is used. We present a design for test (DFT) scheme that offers the accuracy needed to test highquality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy and filter parameters can be shown to be satisfied to within 0.1% accuracy. With this characterization process, a filter can be directly shown to satisfy all specifications that depend on capacitor ratios. We believe the accuracy of our approach is at least an order of magnitude...
A novel capacitance assignment procedure for the design of sensitivity and noiseoptimized SCfilters
 IEEE Trans. Circuits Syst
, 1991
"... A&ru &A novel procedure that determines the capacitor values for a given integratorbased SC network with given capacitor ratios is presented. The procedure optimally distributes a limited capacitance area among the individual circuit capacitors by minimizing the overall capacitor spread while sim ..."
Abstract

Cited by 1 (1 self)
 Add to MetaCart
A&ru &A novel procedure that determines the capacitor values for a given integratorbased SC network with given capacitor ratios is presented. The procedure optimally distributes a limited capacitance area among the individual circuit capacitors by minimizing the overall capacitor spread while simultaneously minimizing either sensitivity or noise. Noise in SC circuits is a function of ideal SC design parameters such as capacitor ratios and capacitance levels and of the technologydependent parameters describing the switches and amplifiers. In our description of the noise performance, we have found a characteristic point which is only a function of SC design parameters and can thus serve as a measure for the noise performance. For its description a closedform expression is used, which has the same form as the corresponding sensitivity measure. With these expressions an efficient capacitance assignment optimization procedure is derived, which is implemented in the computeraided design and optimization program package SCSYN. I.
Design of Low Noise, Low Power Linear CMOS Image Sensors
, 2001
"... The implementation of active pixel based image sensors in CMOS technology is becoming increasingly important forproducing imaging systems that can be manufactured with low cost, low power, simple interface, and with good image quality. The major obstacle in the design of CMOS imagers is Fixed Patter ..."
Abstract
 Add to MetaCart
The implementation of active pixel based image sensors in CMOS technology is becoming increasingly important forproducing imaging systems that can be manufactured with low cost, low power, simple interface, and with good image quality. The major obstacle in the design of CMOS imagers is Fixed Pattern Noise (FPN) and SignaltoNoiseRatio (SNR) of the video output. This research focuses on minimizing FPN and improving SNR in linear CMOS image sensors which are needed in scanning and swiping applications such as nger print sensing, spectroscopy, and medical imaging systems. FPN is reduced in this research through the use of closed loop operational ampli ers in active pixels and through performing Correlated Double Sampling (CDS). SNR is improved by increasing the pixel saturation voltage. This thesis concludes that FPN can be reduced using the closed loop opamp bu ers. The major FPN noise sources are the shot noise from the photodiode, kTC noise from the sampling capacitors, and o set mismatches in the sample and hold ampli ers all of which are not compensated by CDS. Sample and hold ampli er o set mismatch is identi ed as
Sensor Arrays
, 2007
"... A carbon nanotube is considered as a candidate for a nextgeneration chemical sensor. CNT sensors are attractive as they allow roomtemperature sensing of chemicals. From the system perspective, this signifies that the sensor system does not require any micro hotplates, which are one of the major so ..."
Abstract
 Add to MetaCart
A carbon nanotube is considered as a candidate for a nextgeneration chemical sensor. CNT sensors are attractive as they allow roomtemperature sensing of chemicals. From the system perspective, this signifies that the sensor system does not require any micro hotplates, which are one of the major sources of power dissipation in other types of sensor systems. Nevertheless, a poor control of the CNT resistance poses a constraint on the attainable energy efficiency of the sensor platform. An investigation on the CNT sensors shows that the dynamic range of the interface should be 17 bits, while the resolution at each base resistance should be 7 bits. The proposed CMOS interface extends upon the previously published work to optimize the energy performance through both the architecture and circuit level innovations. The 17bit dynamic range is attained by distributing the requirement into a 10bit AnalogtoDigital Converter (ADC) and a 8bit DigitaltoAnalog Converter (DAC). An extra 1bit leaves room for any unaccounted subblock performance error.
Title
, 2002
"... Serietitel och serienummer Title of series, numbering ISSN 14003902 URL för elektronisk version ..."
Abstract
 Add to MetaCart
Serietitel och serienummer Title of series, numbering ISSN 14003902 URL för elektronisk version
MODELING AND SIMULATION OF MOS TRANSISTOR MISMATCH
"... The paper is an overview of MOS transistor mismatch modeling and simulation over the existent literature. The fluctuations of physical parameters and line width are the main causes of mismatch. There are two types of mismatch. Systematic mismatch can be reduced to great extent with proper layout. Di ..."
Abstract
 Add to MetaCart
The paper is an overview of MOS transistor mismatch modeling and simulation over the existent literature. The fluctuations of physical parameters and line width are the main causes of mismatch. There are two types of mismatch. Systematic mismatch can be reduced to great extent with proper layout. Different patterns are available, that are able to reduce from linear to nth order polynomial systematic mismatch. Stochastic mismatch can only be reduced with better process control and larger transistor areas. There are different approaches for calculating the standard deviation representing stochastic mismatch. Simple formulas (e.g. square root of area rule) are most commonly used. With the reducing of the transistor area some new effects should be considerate and more complex formulas are needed. On the other hand correlation functions and frequency domain analysis with spatial spectra give more accurate results. These two approaches are more general but they do not give physical insight and the final layout should be known. Mismatch can be simulated in several ways. Brute force simulation based on MonteCarlo analysis is appropriate for any kind of distribution but it is the most time expensive. Simulations based on small signal analysis are faster because less circuit simulations are needed to calculate the sensitivity. Two different approaches to calculate the sensitivity are presented in this paper.