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An Analysis of Lehmer's Euclidean GCD Algorithm
 Proceedings Of The 1995 International Symposium On Symbolic And Algebraic Computation
, 1995
"... Let u and v be positive integers. We show that a slightly modified version of D. H. Lehmer's greatest common divisor algorithm will compute gcd(u; v) (with u ? v) using at most Of(log u log v)=k + k log v + log u + k 2 g bit operations and O(log u + k2 2k ) space, where k is the number of bits ..."
Abstract

Cited by 7 (3 self)
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Let u and v be positive integers. We show that a slightly modified version of D. H. Lehmer's greatest common divisor algorithm will compute gcd(u; v) (with u ? v) using at most Of(log u log v)=k + k log v + log u + k 2 g bit operations and O(log u + k2 2k ) space, where k is the number of bits in the multiprecision base of the algorithm. This is faster than Euclid's algorithm by a factor that is roughly proportional to k. Letting n be the number of bits in u and v, and setting k = b(log n)=4c, we obtain a subquadratic running time of O(n 2 = log n) in linear space. 1 Introduction Let u and v be positive integers. The greatest common divisor (GCD) of u and v is the largest integer d such that d divides both u and v. The most wellknown algorithm for computing GCDs is the Euclidean Algorithm. Much is known about this algorithm: the number of iterations required is \Theta(log v), and the worstcase running time is \Theta(log u log v), where time is measured in bit operation...
Architectural Analysis of RSA Cryptosystem on FPGA
"... This paper presents different architectures in FPGA based implementations of a public key crypto algorithm RSA algorithm. A hardwarebased cryptographic system is preferred as it provides better security, integrity and is resistant to power analysis attacks [1]. After the complete cryptosystem is ..."
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This paper presents different architectures in FPGA based implementations of a public key crypto algorithm RSA algorithm. A hardwarebased cryptographic system is preferred as it provides better security, integrity and is resistant to power analysis attacks [1]. After the complete cryptosystem is simulated in VERILOG [8] and synthesized for specific XILINX FPGAs, the architecture of the cryptosystem is evolved by performing scheduling in the Data Flow Graph. This way there are two types of architectures realized: – one with high concurrency (which takes lesser number of clock cycles) and the other with maximum sequential operations. Subsequently the size of the key is extended and its effects on the architecture, with respect to area and power consumed, are observed. Finally tradeoff analysis of the various implementations is done.