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26
Symbolic Boolean manipulation with ordered binarydecision diagrams
 ACM Computing Surveys
, 1992
"... Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as grap ..."
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Cited by 894 (13 self)
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Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD
Finding and fixing faults
 Paul (Eds.), 13th Conference on Correct Hardware Design and Verification Methods (CHARME ’05
, 2005
"... Knowing that a program has a bug is good, knowing its location is better, but a fix is best. We present a method to automatically locate and correct faults in a finite state system, either at the gate level or at the source level. We assume that the specification is given in Linear Temporal Logic, a ..."
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Cited by 26 (5 self)
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Knowing that a program has a bug is good, knowing its location is better, but a fix is best. We present a method to automatically locate and correct faults in a finite state system, either at the gate level or at the source level. We assume that the specification is given in Linear Temporal Logic, and state the correction problem as a game, in which the protagonist selects a faulty component and suggests alternative behavior. The basic approach is complete but as complex as synthesis. It also suffers from problems of readability: the correction may add state and logic to the system. We present two heuristics. The first avoids the doubly exponential blowup associated with synthesis by using nondeterministic automata. The second heuristic finds a memoryless strategy, which we show is an NPcomplete problem. A memoryless strategy corresponds to a simple, local correction that does not add any state. The drawback of the two heuristics is that they are not complete unless the specification is an invariant. Our approach is general: the user can define what constitutes a component, and the suggested correction can be an arbitrary combinational function of the current state and the inputs. We show experimental results supporting the applicability of our approach.
BitLevel Analysis of an SRT Divider Circuit
 IN PROCEEDINGS OF THE 33RD DESIGN AUTOMATION CONFERENCE, PAGES 661665, LAS VEGAS, NV
, 1995
"... It is impractical to verify multiplier or divider circuits entirely at the bitlevel using ordered Binary Decision Diagrams (BDDs), because the BDD representations for these functions grow exponentially with the word size. It is possible, however, to analyze individual stages of these circuits using ..."
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Cited by 24 (0 self)
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It is impractical to verify multiplier or divider circuits entirely at the bitlevel using ordered Binary Decision Diagrams (BDDs), because the BDD representations for these functions grow exponentially with the word size. It is possible, however, to analyze individual stages of these circuits using BDDs. Such analysis can be helpful when implementing complex arithmetic algorithms. As a demonstration, we show that Intel could haveused BDDs to detect erroneous lookup table entries in the Pentium(TM) floating point divider. Going beyond verification, we show that bitlevel analysis can be used to generate a correct version of the table.
Errortracer: Design error diagnosis based on fault simulation techniques
 IEEE Trans. CAD
, 1999
"... Abstract—This paper addresses the problem of locating error sources in an erroneous combinational or sequential circuit. We use a fault simulationbased technique to approximate each internal signal’s correcting power. The correcting power of a particular signal is measured in terms of the signal’s ..."
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Cited by 19 (0 self)
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Abstract—This paper addresses the problem of locating error sources in an erroneous combinational or sequential circuit. We use a fault simulationbased technique to approximate each internal signal’s correcting power. The correcting power of a particular signal is measured in terms of the signal’s correctable set, namely, the maximum set of erroneous input vectors or sequences that can be corrected by resynthesizing the signal. Only the signals that can correct every given erroneous input vector or sequence are considered as a potential error source. Our algorithm offers three major advantages over existing methods. First, unlike symbolic approaches, it is applicable for large circuits. Second, it delivers more accurate results than other simulationbased approaches because it is based on a more stringent condition for identifying potential error sources. Third, it can be generalized to identify multiple errors theoretically. Experimental results on diagnosing combinational and sequential circuits with one and two random errors are presented to show the effectiveness and efficiency of this new approach. Index Terms—Design automation, error correction, fault diagnosis, simulation. I.
Incremental synthesis
 In Proc. Intl. Conf. on ComputerAided Design
, 1994
"... A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates fro ..."
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Cited by 17 (1 self)
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A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only. 1.
A Method for Automatic Design Error Location and Correction in Combinational Logic Circuits
 Journal of Electronic Testing: Theory and Applications
, 1996
"... . We present a new diagnostic algorithm, based on backwardpropagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosisoriented test patterns are generated in order to rapidly reduc ..."
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Cited by 14 (4 self)
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. We present a new diagnostic algorithm, based on backwardpropagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosisoriented test patterns are generated in order to rapidly reduce the suspected area where the error lies. The originality of our method is the use of patterns which do not detect the error, in addition to detecting patterns. A theorem shows that, in favourable cases, only two patterns suffice to get a correction. We have implemented the test generation and diagnosis algorithms. Results obtained on benchmarks show that the error is always found, after the application of a small number of test patterns, with an execution time proportional to the circuit size. Keywords: design correctness, design debugging, design error diagnosis 1. Introduction As the design of digital systems is becoming increasingly complex, an undetected design error in the late phas...
Design Error Diagnosis in Digital Circuits with Stuckat Fault Model
 Journal of Microelectronics Reliability. Pergamon Press
"... Abstract. In this paper we describe in detail a new method for the single gatelevel design error diagnosis in combinational circuits. Distinctive features of the method are hierarchical approach (the localizing procedure starts at the macro level and finishes at the gate level), use of stuckat fau ..."
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Cited by 11 (3 self)
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Abstract. In this paper we describe in detail a new method for the single gatelevel design error diagnosis in combinational circuits. Distinctive features of the method are hierarchical approach (the localizing procedure starts at the macro level and finishes at the gate level), use of stuckat fault model (it is mapped into design error domain only in the end), and design error diagnostic procedure that uses only test patterns generated by conventional gatelevel stuckat fault test pattern generators (ATPG). No special diagnostic tests are used because they are much more time consuming. Binary decision diagrams (BDD) are exploited for representing and localizing stuckat faults on the higher signal path level. On the basis of detected faulty signal paths, suspected stuckat faults at gate inputs are calculated, and then mapped into suspected design error(s). This method is enhanced compared to our previous work. It is applicable to redundant circuits and allows using incomplete tests for error diagnosis. Experimental data on ISCAS benchmark circuits shows the advantage of the proposed method compared to the known algorithms of design error diagnosis. 1.
Design Error Diagnosis in Sequential Circuits
 Proc. Correct Hardware Design and Verification Methods, CHARME'95, Lecture
, 1995
"... . We present a new diagnostic algorithm for localising design errors in sequential circuits. The specification and the implementation may have different number of state variables, and different state encoding. The algorithm is based on the new concept of possible next states describing the possible ..."
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Cited by 11 (4 self)
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. We present a new diagnostic algorithm for localising design errors in sequential circuits. The specification and the implementation may have different number of state variables, and different state encoding. The algorithm is based on the new concept of possible next states describing the possible states of the circuit due to the existence of the error. Results obtained on benchmark circuits show that the error is always found, with an execution time proportional to the product of the circuit size, and the length of the test sequences used. 1 Introduction Although automated design tools are routinely used for digital circuits synthesis, manual changes are still being done to improve the performance, to obtain more compact structures, or to carry on small specification changes; doing so, the insertion of an unintentional error is very likely to happen. Another source of design errors is the presence of software bugs in the automated design and optimization tools. Therefore, formal ve...
Error Correction Based on Verification Techniques
 IN PROCEEDINGS OF THE 33RD DESIGN AUTOMATION CONFERENCE (DAC
, 1996
"... In this paper, we address the problem of correcting a combinational circuit that is an incorrect implementation of a given specification. Most existing errorcorrection approaches can only handle circuits with certain types of errors. Here, we propose a general approach that can correct a circuit wi ..."
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Cited by 9 (2 self)
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In this paper, we address the problem of correcting a combinational circuit that is an incorrect implementation of a given specification. Most existing errorcorrection approaches can only handle circuits with certain types of errors. Here, we propose a general approach that can correct a circuit with multiple errors without assuming any error model. We identify internal equivalent pairs to narrow down the possible error locations using local BDD's with dynamic support. We also employ a technique called backsubstitution to correct the circuit incrementally. This approach can also be used to verify circuit equivalence. The experimental results of correcting fully SISoptimized benchmark circuits with a number of injected errors will be presented.
Mince: matching instructions using combinational equivalence for extensible processor
 In Conference on Design, Automation and Test in Europe
, 2004
"... Designing customextensible instructions for Extensible Processors 1 is a computationally complex task because of the large design space. The task of automatically matching candidate instructions in an application (e.g. written in a highlevel language) to a predesigned library of extensible instru ..."
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Cited by 7 (1 self)
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Designing customextensible instructions for Extensible Processors 1 is a computationally complex task because of the large design space. The task of automatically matching candidate instructions in an application (e.g. written in a highlevel language) to a predesigned library of extensible instructions is especially challenging. Previous approaches have focused on identifying extensible instructions (e.g. through profiling), synthesizing extensible instructions, estimating expected performance gains etc. In this paper we introduce our approach of automatically matching extensible instructions as this key step is missing in automating the entire design flow of an ASIP with extensible instruction capabilities. Since matching using simulation is practically infeasible (simulation time), and traditional pattern matching approaches would not yield reliable results (ambiguity related to a functionally equivalent code that can be represented in many different ways), we adopt combinational equivalence checking. Our MINCE tool as part of our ASIP design flow consists of a translator, a filtering algorithm and a combinational equivalence checking tool. We report matching times of extensible instructions that are 7.3x faster on average (using Mediabench applications) compared to the best known approaches to the problem (partial simulations). In all our experiments MINCE matched correctly and the outcome of the matching step yielded an average speedup of the application of 2.47x. As a summary, our work represents a key step towards automating the whole design flow of an ASIP with extensible instruction capabilities. 1