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45
Symbolic Boolean manipulation with ordered binarydecision diagrams
 ACM Computing Surveys
, 1992
"... Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as grap ..."
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Cited by 894 (13 self)
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Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD
Efficient implementation of a BDD package
 In Proceedings of the 27th ACM/IEEE conference on Design autamation
, 1991
"... Efficient manipulation of Boolean functions is an important component of many computeraided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementat ..."
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Cited by 454 (10 self)
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Efficient manipulation of Boolean functions is an important component of many computeraided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementation of the ifthenelse (ITE) operator. A hash table is used to maintain a strong carwnical form in the ROBDD, and memory use is improved by merging the hash table and the ROBDD into a hybrid data structure. A memory funcfion for the recursive ITE algorithm is implemented using a hashbased cache to decrease memory use. Memory function efficiency is improved by using rules that detect. when equivalent functions are computed. The usefulness of the package is enhanced by an automatic and lowcost scheme for rec:ycling memory. Experimental results are given to demonstrate why various implementation tradeoffs were made. These results indicate that the package described here is significantly faster and more memoryefficient than other ROBDD implementations described in the literature. 1
Verification of synchronous sequential machines based on symbolic execution, Automatic Verification Methods for Finite State Systems
, 1989
"... This paper presents an original method to compare two synchronous sequential machines. The method consists in a breadth first traversal of the product machine during which symbolic expressions of its observable behaviour are computed. ~Iqae method uses formal manipulations on boolean functions to av ..."
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Cited by 159 (3 self)
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This paper presents an original method to compare two synchronous sequential machines. The method consists in a breadth first traversal of the product machine during which symbolic expressions of its observable behaviour are computed. ~Iqae method uses formal manipulations on boolean functions to avoid the state enumeration and diagram construction. For this purpose, new algorithms on boolean functions represented by Typed Decision Graphs has been defined. 1.
SCIP: solving constraint integer programs
, 2009
"... Constraint integer programming (CIP) is a novel paradigm which integrates constraint programming (CP), mixed integer programming (MIP), and satisfiability (SAT) modeling and solving techniques. In this paper we discuss the software framework and solver SCIP (Solving Constraint Integer Programs), wh ..."
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Cited by 57 (0 self)
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Constraint integer programming (CIP) is a novel paradigm which integrates constraint programming (CP), mixed integer programming (MIP), and satisfiability (SAT) modeling and solving techniques. In this paper we discuss the software framework and solver SCIP (Solving Constraint Integer Programs), which is free for academic and noncommercial use and can be downloaded in source code. This paper gives an overview of the main design concepts of SCIP and how it can be used to solve constraint integer programs. To illustrate the performance and flexibility of SCIP, we apply it to two different problem classes. First, we consider mixed integer programming and show by computational experiments that SCIP is almost competitive to specialized commercial MIP solvers, even though SCIP supports the more general constraint integer programming paradigm. We develop new ingredients that improve current MIP solving technology. As a second application, we employ SCIP to solve chip design verification problems as they arise in the logic design of integrated circuits. This application goes far beyond traditional MIP solving, as it includes several highly nonlinear constraints, which can be handled nicely within the constraint integer programming framework. We show anecdotally how the different solving techniques from MIP, CP, and SAT work together inside SCIP to deal with such constraint classes. Finally, experimental results show that our approach outperforms current stateoftheart techniques for proving the validity of properties on circuits containing arithmetic.
Verification Techniques for Cache Coherence Protocols.
, 1997
"... ion and Specification Using FSMs Although there is a variety of ways to specify a protocol model, we are interested in methodologies that employ finite state machines (FSMs) to form protocol models. Because cache protocols are essentially composed of component processes such as memory and cache cont ..."
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Cited by 38 (0 self)
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ion and Specification Using FSMs Although there is a variety of ways to specify a protocol model, we are interested in methodologies that employ finite state machines (FSMs) to form protocol models. Because cache protocols are essentially composed of component processes such as memory and cache controllers that exchange messages and respond to "events" generated by processors, a finite state machine model with such "events" as its inputs is a natural model. Specifically, we focus on verifying cache protocols where the behavior of an individual protocol component C is modeled as a finite state machine [FSM.sub.c] and the protocol machine is composed of all [FSM.sub.c]s. Inputs to these machines are processorgenerated events and messages for maintaining data consistency. In general, the protocol models are abstracted representations. They are often kept simple to make the complexity of verification manageable, while preserving properties of interest. It is clear that the quality of a ve...
Formally Verifying a Microprocessor Using a Simulation Methodology
, 1994
"... Formal verification is becoming a useful means of validating designs. We have developed a methodology for formally verifying dataintensive circuits (e.g., processors) with sophisticated timing (e.g., pipelining) against highlevel declarative specifications. Previously, formally verifying a micropro ..."
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Cited by 26 (4 self)
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Formal verification is becoming a useful means of validating designs. We have developed a methodology for formally verifying dataintensive circuits (e.g., processors) with sophisticated timing (e.g., pipelining) against highlevel declarative specifications. Previously, formally verifying a microprocessor required the use of an automatic theorem prover, but our technique requires little more than a symbolic simulator. We have formally verified a preexisting 16bit CISC microprocessor circuit extracted from the fabricated layout. Introduction Previously, symbolic switchlevel simulation has been used to verify some small or simple dataintensive circuits (RAMs, stacks, register files, ALUs, and simple pipelines) [2, 3]. In doing so, the necessary simulation patterns were developed by hand or by using adhoc techniques, and it was then argued that the patterns were sufficient, and that their generation could be automated. We have developed sufficient theory to fully support such claims...
DDDFM9001: Derivation of a Verified Microprocessor
, 1994
"... Derivation and verification represent alternate approaches to design. Derivation aims at deriving a "correct by construction" design while verification aims at constructing a post factum "proof of correctness" for a design. However, as researchers and engineers gain design experi ..."
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Cited by 22 (6 self)
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Derivation and verification represent alternate approaches to design. Derivation aims at deriving a "correct by construction" design while verification aims at constructing a post factum "proof of correctness" for a design. However, as researchers and engineers gain design experience in a formal framework, both approaches are emerging as interdependent facets of design. The thesis of this work is that alternate forms of formal reasoning must be integrated if formal methods are to support the natural analytical and generative reasoning that takes place in engineering practice. As a vehicle for this research, the DDD digital design derivation system was implemented to study formal hardware design in an algebraic framework. DDD is a firstorder transformation system which mechanizes a basic design algebra for synthesizing digital circuit descriptions from highlevel functional specifications. The system is a collection of correctness preserving transformations that promote a topdown desig...
A Logically Complete Reasoning Maintenance System Based on a Logical Constraint Solver
 in Proc. of IJCAI'91
, 1991
"... This paper presents a logically complete assumption based truth maintenance system (ATMS) that is part of a complex blast furnace computer aided piloting system [ 5 ] . This system is built on an efficient and logically complete propositional constraint solver that has been successfully used for ind ..."
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Cited by 22 (6 self)
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This paper presents a logically complete assumption based truth maintenance system (ATMS) that is part of a complex blast furnace computer aided piloting system [ 5 ] . This system is built on an efficient and logically complete propositional constraint solver that has been successfully used for industrial applications in computer aided design. 1 Introduction A reasoning maintenance system (RMS) is a critical part of a reasoning system, since it is responsible for assuring that the inferences made by that system are valid. The reasoning system provides the RMS with information about each inference it performs, and in return the RMS provides the reasoning system with information about the whole set of inferences. Several implementations of reasoning maintenance systems have been proposed in the past, remarkable ones being Doyle's truth maintenance system (TMS) [ 6 ] , and De Kleer's assumptionbased truth maintenance system (ATMS) [ 7 ] . Both of them suffer from some limitations. The...
Dependability Assessment Using Binary Decision Diagrams (BDDs)
"... ... algorithm which incorporates coverage modeling into a BDD solution of a combinatorial model. BDDs, which do not use cutsets to generate system unreliability, may be used to nd exact solutions for extremely large systems. The DREDD algorithm takes advantage of the e ciency of the BDD solution app ..."
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Cited by 19 (2 self)
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... algorithm which incorporates coverage modeling into a BDD solution of a combinatorial model. BDDs, which do not use cutsets to generate system unreliability, may be used to nd exact solutions for extremely large systems. The DREDD algorithm takes advantage of the e ciency of the BDD solution approach and increases the accuracy of a combinatorial model by including consideration of (possibly) imperfect coverage. The usefulness of combinatorial models, long appreciated for their logical structure and concise representational form, is extended to include many fault tolerant systems previously thought to require more complicated analysis techniques in order to include coverage modeling. In this paper, the DREDD approach is presented and applied to the analysis of two sample systems, the F18 ight control system and a fault tolerant multistage interconnection network.
Verity  a Formal Verification Program for Custom CMOS Circuits
 IBM JOURNAL OF RESEARCH AND DEVELOPMENT
, 1994
"... In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of current generation processors and the necessity for manual designer intervention throughout the design process, proving design correc ..."
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Cited by 19 (5 self)
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In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of current generation processors and the necessity for manual designer intervention throughout the design process, proving design correctness is a major concern. In this paper we discuss Verity, a formal verification program for symbolically proving the equivalence between a highlevel design specification and a MOS transistorlevel implementation. Verity