DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, general-purpose registers. Hence, it is necessary to use address registers and perform address arithmetic to access automatic variables. Subsuming the address arithmetic into auto-increment and auto-decrement modes improves the size of the generated code. In this paper we present a formulation of the problem of optimal storage assignment such that explicit instructions for address arithmetic are minimized. We prove that for the case of a single address register the decision problem is NP-complete. We then generalize the problem to multiple address registers. For both cases heuristic algorithms are given. Our experimental results indicate an improvement of 3 % to 20 % in code size. 1

... This paper introduces the reader to various aspects of co-design. We highlight the commonalities and point out the differences in various co-design problems in some application areas. Co-design issues and their relationship to classical system implementation tasks are discussed to help the reader develop a perspective on modern digital system design that relies on computer-aided design (CAD) tools and methods.

The AVIV retargetable code generator produces optimized machine code for target processors with different instruction set architectures. AVIV optimizes for minimum code size. Retargetable code generation requires the development of heuristic algorithms for instruction selection, resource allocation, and scheduling. AVIV addresses these code generation subproblems concurrently, whereas most current code generation systems address them sequentially. It accomplishes this by converting the input application to a graphical (Split-Node DAG) representation that specifies all possible ways of implementing the application on the targetprocessor. The information embedded in this representation is then used to set up a heuristic branch-and-bound step that performs functional unit assignment, operation grouping, register bank allocation, and scheduling concurrently. While detailed register allocation is carried out as a second step, estimates of register requirements are generated during the fir...

INTRODUCTION Embedded microprocessors are a common feature in modern electronic systems due to the advantages they offer in terms of flexibility, reduction in design time, and full-custom layout quality [Marwedel and Goosens 1995]. Embedded processors commonly used in the market today can be classified into two categories: application-specific processors, such as those in the DSP domain (e.g., TMS320 series from Texas Instruments), and generalpurpose processors (e.g., the CW4000 series from LSI Logic and the ARM series from Advanced RISC Machines). In this article, we concentrate on This work was partially supported by grants from ARPA (MDA904-96-C-1472), NSF(CDA9422095) , and ONR(N00014-93-1-1348). Authors' address: Department of Information and Computer Science, University of California, Irvine, CA 92697; email: #ppanda@ics.uci.edu#. Permission to make digital / hard copy of part or all of this work for personal or classroom use is grante

DSP algorithms in most cases are subject to hard real-time constraints. In case of programmable DSP processors, meeting those constraints must be ensured by appropriate code generation techniques. For processors offering instruction-level parallelism, the task of code generation includes code compaction. The exact timing behavior of a DSP program is only known after compaction. Therefore, real-time constraints should be taken into account during the compaction phase. While most known DSP code generators rely on rigid heuristics for that phase, this paper proposes a novel approach to local code compaction based on an Integer Programming model, which obeys exact timing constraints. Due to a general problem formulation, the model also obeys encoding restrictions and possible side effects. 1 1 Introduction & related work Design requirements for embedded systems including DSP functionality strongly differ from those for interactive environments such as workstations. While in the latter ca...

In this paper we address the problem of code generation for basic blocks in heterogeneous memory-register DSP processors. We propose a new a technique, based on register-transfer paths, that can be used for efficiently dismantling basic block DAGs (Directed Acyclic Graphs) into expression trees. This approach builds on recent results which report optimal code generation algorithm for expression trees for these architectures. This technique has been implemented and experimentally validated for the TMS320C25, a popular fixed point DSP processor. The results show that good code quality can be obtained using the proposed technique. An analysis of the type of DAGs found in the DSPstone benchmark programs reveals that the majority of basic blocks in this benchmark set are expression trees and leaf DAGs. This leads to our claim that tree based algorithms, like the one described in this paper, should be the technique of choice for basic block code generation with heterogeneous memoryregister a...

This paper presents a new code placement method for embedded software to maximize hit ratios of instruction caches. We formulate the code placement problem as an integer linear programming problem. One of the advantages of our method is that code can be moved beyond boundaries of functions, so that code placement is optimized globally. Experimental results show our method achieves 35% (max 45%) reduction of cache misses. 1 Introduction In design of an embedded system, several design goals such as high performance, low cost, and low power consumption of the system must be achieved simultaneously. But these design goals are often mutually exclusive. Consider a system which consists of a processor core, main memories and cache memories. The performance of the system is expressed as the following formula: Performance = 1 Execution time = F IC 2 (CPI +(10CHR)2CMP) (1) where F , IC,CPI,CHR and CMP denotes the clock frequency, the instruction count to be executed, clock cycles per in...

In this paper we present a uni ed frontend for retargetable compilers that performs analysis of the target processor model. Our approach bridges the gap between structural and behavioral processor models for retargetable compilation. This is achieved by means of instruction set extraction. The extraction technique is based on a BDD data structure which signi cantly improves control signal analysis in the target processor compared to previous approaches. 1 1

Application domain specific DSP cores are becoming increasingly popular due to their advantageous trade--off between flexibility and cost. However, existing code generation methods are hampered by the combination of tight timing and resource constraints, imposed by the throughput requirements of DSP algorithms together with a fixed core architecture. In this paper, we present a method to model resource and instruction set conflicts uniformly and statically before scheduling. With the model we exploit the combination of all possible constraints, instead of being hampered by them. The approach results in an exact and run time efficient method to solve the instruction scheduling problem, which is illustrated by real life examples. 1. Introduction Predefined DSP cores which are tuned towards specific application domains are becoming increasingly popular, due to their advantageous trade--off between flexibility and cost. Such a core is relatively flexible in comparison to an ASIC: differen...

This paper discusses design technology issues for embedded systems using processor cores, with a focus on software compilation tools. Architectural characteristics of contemporary processor cores are reviewed and tool requirements are formulated. This is followed by a comprehensive survey of both existing and new software compilation techniques that are considered important in the context of embedded processors