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Declustering problems are well-known in the databases for parallel computing environments. In this paper, we propose a new similarity-based technique for declustering data. The proposed method can adapt to the available information about query distribution (e.g. size, shape and frequency) and can work with alternative atomic data-types. Furthermore, the proposed method is flexible and can work with alternative data distributions, data sizes and partition-size constraints. The method is based on max-cut partitioning of a similarity graph defined over the given set of data, under constraints on the partition sizes. It maximizes the chances that a pair of atomic data-items that are frequently accessed together by queries are allocated to distinct disks. We describe the application of the proposed method to parallelizing Grid Files at the data page level. Detailed experiments in this context show that the proposed method adapts to query distribution and data distribution, and tha...

We give new, effective algorithms for k-way circuit partitioning in the two regimes of k ø n and k = \Theta(n), where n is the number of modules in the circuit. We show that partitioning an appropriately designed geometric embedding of the netlist, rather than a traditional graph representation, yields improved results as well as large speedups. We derive d- dimensional geometric embeddings of the netlist via (i) a new "partitioning-specific" net model for constructing the Laplacian of the netlist, and (ii) computation of d eigenvectors of the netlist Laplacian; we then apply (iii) fast top-down and bottom-up geometric clustering methods. 1 Preliminaries In top-down layout synthesis of complex VLSI systems, the goal of partitioning/clustering is to reveal the natural circuit structure, via a decomposition into k subcircuits which minimizes connectivity between subcircuits. A generic problem statement is as follows: k-Way Partitioning: Given a circuit netlist G = (V; E) with jV j...

Abstract – This paper considers the problem of obtaining a minimum–cost partitioning of a large logic circuit into a collection of subcircuits implementable with devices selected from a given library. Each device in the library may have a different price, size, and terminal capacity. We propose a multi–way partitioning algorithm based on a recursive application of the Fiduccia-Mattheyses bipartitioning heuristic, extended to handle (a) the overall goal of the cost minimization and (b) the constraints reflecting the limitations on the capacity of FPGA chips. The experimental implementation of the proposed algorithm has exhibited a very encouraging performance, producing solutions close to the theoretical minima calculated for many benchmark circuits. I. INTRODUCYIIION

Spectral geometric embeddings of a circuit netlist can lead to fast, high quality multi-way partitioning solutions. Furthermore, it has been shown that d-dimensional spectral embeddings (d ? 1) are a more powerful tool than single-eigenvector embeddings (d = 1) for multi-way partitioning [2] [4]. However, previous methods cannot fully utilize information from the spectral embedding while optimizing netlist-dependent objectives. This work introduces a new multi-way circuit partitioning algorithm called DP-RP. We begin with a d-dimensional spectral embedding from which a 1-dimensional ordering of the modules is obtained using a spacefilling curve. The 1dimensional ordering retains useful information from the multi-dimensional embedding while allowing application of efficient algorithms. We show that for a new Restricted Partitioning formulation, dynamic programming efficiently finds optimal solutions in terms of Scaled Cost [4] and can transparently handle userspecified cluster size co...

Abstract-Partitioning is an important step in the top-down design of large complicated integrated circuits. In this paper, a cut and reported 38 % average reduction in nets cut when compared with those of the F&M [l] method. However, simple yet effective partitioning technique is described. It is based on the clustering of “closely ” connected cells and the gradual enforcement of size-constraints. At the beginning, clusters are formed in the bottom-up fashion to reduce the problem size. Then the clusters are partitioned using several different parameters to experimental results show that our method works better with the exact cost function as explained in Section V. Another method [6] used “level gain ” to predict the cost changes when moving each cell and Sanchis [7] adapted this find a good starting point. The best result achieved during the cluster partitioning is used as the initial solution for the lower level partitioning. The gradual constraint enforcement technique is used to cope with the local minimum problems. It allows cells or clusters to move with more freedom among the subsets during earlier iterations and thus may effectively find a near model to multiple-way partitioning. In [8], [9], an evolutionbased approach was reported which outperformed the F&M method by 27 % and a version of annealing-based algorithm with an efficient annealing schedule [lo] by 54 % on the average. These methods move or exchange nodes so that the optimum solution. Several experimental results show that the new partitioning technique produces favorable results. In particular, our method outperforms the F&M method [l] by more than 60% in the number of crossing nets on the average. size constraints are always satisfied. Recently, several authors reported a ratio-cut [ 1 11 approach which does not impose hard limits on the subset sizes. In these methods, subset sizes may be significantly different when the I.

In this paper, we demonstrate that the "dual" intersection graph of the netlist strongly captures circuit properties relevant to partitioning. We apply this transformation within an existing testbed that uses an eigenvector computation to derive a linear ordering of nets, rather than modules [12]. We then find a good module partition with respect to the ratio cut metric [23] via a sequence of incremental independent-set computations in bipartite graphs derived from the net ordering. An efficient matching-based algorithm called IG-Match was tested on MCNC benchmark circuits as well as additional industry examples. Results are very encouraging: the algorithm yields an average of 28.8% improvement over the results of [23]. The intersection graph representation also yields speedups over, e.g., the method of [11], due to additional sparsity in the netlist representation. 1 1 Preliminaries A standard model for VLSI layout associates a graph G = (V; E) with the circuit netlist; vertices in...

Abstract — This paper considers the problem of partitioning a large logic circuit into a collection of subcircuits each of which is implemented with a device from a specific (FPGA) library. The objective function that we minimize is not only the total cost of devices to be used in the partition but also the size of the interconnect between the devices. We introduce the concept of functional replication and a unified cost model for min-cut partitioning with replication. A prototype implementation demonstrates the feasibility of the approach, based on experimental results with a set of large benchmark circuits. I.

In this paper, we introduce a new recursive partitioning paradigm PROP which combines partitioning, replication, optimization, to be followed by another recursion of partitioning, etc. We measure the quality of partitions in terms of total device cost, logic and terminal utilization, and critical path delay. Traditionally, the minimum lower bound into which a given netlist can be partitioned is determined by disregarding the logic interconnect while distributing the logic nodes into a minimum number of devices. PROP paradigm challenges this assumption by demonstrating feasible partitions of some large netlists such that the number of device partitions is smaller than minimum lower bounds postulated initially. Overall, we report consistent reductions in the total number of partitions for a wide range of combinational and sequential circuit benchmarks while, on the average, reducing critical path delay as well. I. Introduction Much of research on partitioning algorithms considers minim...

This paper presents effective algorithms for multi-way partitioning. Confirming ideas originally due to Hall [27], we demonstrate that geometric embeddings of the circuit netlist can lead to high-quality k-way partitionings. The netlist embeddings are derived via the computation of d eigenvectors of the Laplacian for a graph representation of the netlist. As [27] did not specify how to partition such geometric embeddings, we explore various geometric partitioning objectives and algorithms, and find that they are limited because they do not integrate topological information from the netlist. Thus, we also present a new partitioning algorithm that exploits both the geometric embedding and netlist information, as well as a Restricted Partitioning formulation that requires each cluster of the k-way partitioning to be contiguous in a given linear ordering. We begin with a d-dimensional spectral embedding and construct a heuristic 1-dimensional ordering of the modules (combining spacefillin...