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Circuit Clustering for Delay Minimization under Area and Pin Constraints
 IEEE TRANS. ON COMPUTERAIDED DESIGN
, 1995
"... We consider the problem of circuit partitioning for multiplechip implementation. One motivation for studying this problem is the current needs of good partitioning tools for implementing a circuit on multiple FPGA chips. We allow replication of logic gates as it would reduce circuit delay. Circu ..."
Abstract

Cited by 24 (1 self)
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We consider the problem of circuit partitioning for multiplechip implementation. One motivation for studying this problem is the current needs of good partitioning tools for implementing a circuit on multiple FPGA chips. We allow replication of logic gates as it would reduce circuit delay. Circuit partitioning with replication of logic gates is also called circuit clustering. In this paper, we present a circuit clustering algorithm that minimizes circuit delay subject to area and pin constraints on each chip, under the general delay model. We developed a repeated network cut technique to find a cluster that is bounded by both area and pin constraints. Our algorithm is optimal under either the area constraint only or the pin constraint only. We tested our algorithm on a set of benchmark circuits and consistently obtained optimal or nearoptimal results.
On the Maximum Degree of Minimum Spanning Trees (Extended Abstract)
 IN PROC. ACM SYMP. COMPUTATIONAL GEOMETRY, STONY
, 1994
"... Motivated by practical VLSI applications, we study the maximum vertex degree in a minimum spanning tree (MST) under arbitrary L p metrics. We show that the maximum vertex degree in a maximumdegree L p MST equals the Hadwiger number of the corresponding unit ball. We then determine the maximum verte ..."
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Motivated by practical VLSI applications, we study the maximum vertex degree in a minimum spanning tree (MST) under arbitrary L p metrics. We show that the maximum vertex degree in a maximumdegree L p MST equals the Hadwiger number of the corresponding unit ball. We then determine the maximum vertex degree in a minimumdegree L p MST; towards this end, we define the MST number, which is closely related to the Hadwiger number. We bound Hadwiger and MST numbers for arbitrary L p metrics, and focus on the L 1 metric, where little was known. We show that the MST number of a diamond is 4, and that for the octahedron the Hadwiger number is 18 and the MST number is either 13 or 14. We also give an exponential lower bound on the MST number for an L p unit ball. Implications to L p minimum spanning trees and related problems are explored.
BIPARTITIONING into OVERLAPPING sets
, 1994
"... We consider the problem of partitioning a graph G = (V; E) into two sets V 1 and V 2 such that jV 1 " V 2 j is no more than an integer d, and such that P u2V 1 \GammaV 2 ;v2V 2 \GammaV 1 (u; v) is minimized. We show that this problem is NPhard in general. It remains NPhard if jV 1 j = jV 2 ..."
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We consider the problem of partitioning a graph G = (V; E) into two sets V 1 and V 2 such that jV 1 " V 2 j is no more than an integer d, and such that P u2V 1 \GammaV 2 ;v2V 2 \GammaV 1 (u; v) is minimized. We show that this problem is NPhard in general. It remains NPhard if jV 1 j = jV 2 j, or if we insist that, for any bipartition, v 1 2 V 1 and v 2 2 V 2 for two specific nodes v 1 ; v 2 2 V . The problem variation in which either jV 1 j = jV 2 j or jV 1 j = k, k 2 Z + , finds important applications in VLSI layout and hypertext partitioning. We examine the latter problems on special cases of graphs which have been examined in the literature for similar partitioning problems. We present polynomial time algorithms for the special cases of (a) seriesparallel graphs, and (b) solid grids. Keywords: Algorithms, VLSI Layout, graph partitioning, solid grids, seriesparallel graphs. 1 Introduction In this paper, we first consider the problem of partitioning a graph G = (V; E) of n n...