Results 1 
6 of
6
Closing the Gap: NearOptimal Steiner Trees in Polynomial Time
 IEEE Trans. ComputerAided Design
, 1994
"... The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NPhard, and the best performing MRST heuristic to date is the Iterated 1Steiner (I1S) method recently proposed by Kahng and Robins. In ..."
Abstract

Cited by 42 (13 self)
 Add to MetaCart
The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NPhard, and the best performing MRST heuristic to date is the Iterated 1Steiner (I1S) method recently proposed by Kahng and Robins. In this paper we develop a straightforward, efficient implementation of I1S, achieving a speedup factor of three orders of magnitude over previous implementations. We also give a parallel implementation that achieves nearlinear speedup on multiple processors. Several performanceimproving enhancements enable us to obtain Steiner trees with average cost within 0.25% of optimal, and our methods produce optimal solutions in up to 90% of the cases for typical nets. We generalize I1S and its variants to three dimensions, as well as to the case where all the pins lie on k parallel planes, which arises in, e.g., multilayer routing. Motivated by the goal of reducing the running times of our algorith...
LowDegree Minimum Spanning Trees
 Discrete Comput. Geom
, 1999
"... Motivated by practical VLSI routing applications, we study the maximum vertex degree of a minimum spanning tree (MST). We prove that under the Lp norm, the maximum vertex degree over all MSTs is equal to the Hadwiger number of the corresponding unit ball; we show an even tighter bound for MSTs where ..."
Abstract

Cited by 22 (1 self)
 Add to MetaCart
Motivated by practical VLSI routing applications, we study the maximum vertex degree of a minimum spanning tree (MST). We prove that under the Lp norm, the maximum vertex degree over all MSTs is equal to the Hadwiger number of the corresponding unit ball; we show an even tighter bound for MSTs where the maximum degree is minimized. We give the bestknown bounds for the maximum MST degree for arbitrary Lp metrics in all dimensions, with a focus on the rectilinear metric in two and three dimensions. We show that for any finite set of points in the rectilinear plane there exists an MST with maximum degree of at most 4, and for threedimensional rectilinear space the maximum possible degree of a minimumdegree MST is either 13 or 14. 1 Introduction Minimum spanning tree (MST) construction is a classic optimization problem for which several efficient algorithms are known [9] [15] [19]. Solutions of many other problems hinge on the construction of an MST as an intermediary step [4], with th...
ThreeDimensional FieldProgrammable Gate Arrays
, 1995
"... Motivated by improving FPGA performance, we propose a new threedimensional (3D) FPGA architecture, along with a fabrication methodology. We analyze the expected manufacturing yield, and raise several physicaldesign issues in the new 3D paradigm. Our techniques also have good implications for resou ..."
Abstract

Cited by 18 (5 self)
 Add to MetaCart
Motivated by improving FPGA performance, we propose a new threedimensional (3D) FPGA architecture, along with a fabrication methodology. We analyze the expected manufacturing yield, and raise several physicaldesign issues in the new 3D paradigm. Our techniques also have good implications for resource utilization, physical size, and power consumption. 1 Introduction Fieldprogrammable gate arrays (FPGAs) are (re)programmable chips that can implement arbitrary logic. FPGAs provide designers with a faster and more economical design cycle [6]. However, this flexibility is achieved at the cost of a substantial performance penalty, due primarily to interconnect delay. This penalty can account for over 70% of the clock cycle period [14, 16]. We propose a new threedimensional (3D) FPGA architecture. The shorter average interconnect distance in a 3D FPGA (i.e., O(n 1 3 ) for an nblock 3D FPGA vs. O(n 1 2 ) in the 2D case) implies shorter signal propagation delay, while the increased ...
Placement and Routing for ThreeDimensional FPGAs
, 1996
"... We explore physical layout for a threedimensional (3D) FPGA architecture. For placement, we introduce a topdown partitioning technique based on rectilinear Steiner trees; we then employ a onestep router to produce the final layout. Experimental results indicate that our approach produces effective ..."
Abstract

Cited by 14 (2 self)
 Add to MetaCart
We explore physical layout for a threedimensional (3D) FPGA architecture. For placement, we introduce a topdown partitioning technique based on rectilinear Steiner trees; we then employ a onestep router to produce the final layout. Experimental results indicate that our approach produces effective 3D layouts, using considerably shorter average interconnect distance than is achievable with conventional 2D FPGA's of comparable size. 1 Introduction A fieldprogrammable gate array (FPGA) is a flexible and reusable design alternative to custom integrated circuits. Using FPGAs, digital designs can be quickly implemented and emulated in hardware, which enables a faster, more economical design cycle [8]. The flexible logic and connection resources of FPGAs allow different designs to be implemented on the same hardware. However, this versatility comes at the expense of a substantial performance penalty due primarily to signal delay through the programmable routing switches. This delay can a...
INVITED PAPER InterconnectBased Design Methodologies for ThreeDimensional Integrated Circuits
"... Vertical integration is a novel communications paradigm where interconnect design is a primary focus. By Vasilis F. Pavlidis, Student Member IEEE, and Eby G. Friedman, Fellow IEEE ABSTRACT  Design techniques for threedimensional (3D) ICs considerably lag the significant strides achieved in 3D ma ..."
Abstract
 Add to MetaCart
Vertical integration is a novel communications paradigm where interconnect design is a primary focus. By Vasilis F. Pavlidis, Student Member IEEE, and Eby G. Friedman, Fellow IEEE ABSTRACT  Design techniques for threedimensional (3D) ICs considerably lag the significant strides achieved in 3D manufacturing technologies. Advanced design methodologies for twodimensional circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3D circuits are necessary. These 3D design methodologies should support robust and reliable 3D circuits while considering different forms of vertical integration, such as systeminpackage and 3D ICs with fine grain vertical interconnections. Global signaling issues, such as clock and power distribution networks, are further exacerbated
On the Maximum Degree of Minimum Spanning Trees (Extended Abstract)
 IN PROC. ACM SYMP. COMPUTATIONAL GEOMETRY, STONY
, 1994
"... Motivated by practical VLSI applications, we study the maximum vertex degree in a minimum spanning tree (MST) under arbitrary L p metrics. We show that the maximum vertex degree in a maximumdegree L p MST equals the Hadwiger number of the corresponding unit ball. We then determine the maximum verte ..."
Abstract
 Add to MetaCart
Motivated by practical VLSI applications, we study the maximum vertex degree in a minimum spanning tree (MST) under arbitrary L p metrics. We show that the maximum vertex degree in a maximumdegree L p MST equals the Hadwiger number of the corresponding unit ball. We then determine the maximum vertex degree in a minimumdegree L p MST; towards this end, we define the MST number, which is closely related to the Hadwiger number. We bound Hadwiger and MST numbers for arbitrary L p metrics, and focus on the L 1 metric, where little was known. We show that the MST number of a diamond is 4, and that for the octahedron the Hadwiger number is 18 and the MST number is either 13 or 14. We also give an exponential lower bound on the MST number for an L p unit ball. Implications to L p minimum spanning trees and related problems are explored.