This note discusses the main issues in performing correctly rounded decimal-to-binary and binary-to-decimal conversions. It reviews recent work by Clinger and by Steele and White on these conversions and describes some efficiency enhancements. Computational experience with several kinds of arithmetic suggests that the average computational cost for correct rounding can be small for typical conversions. Source for conversion routines that support this claim is available from netlib.

Sometimes an optimization problem can be simplified to a form that is faster to solve. Indeed, sometimes it is convenient to state a problem in a way that admits some obvious simplifications, such as eliminating fixed variables and removing constraints that become redundant after simple bounds on the variables have been updated appropriately. Because of this convenience, the AMPL modeling system includes a "presolver" that attempts to simplify a problem before passing it to a solver. The current AMPL presolver carries out all the primal simplifications described by Brearely et al. in 1975. This paper describes AMPL's presolver, discusses reconstruction of dual values for eliminated constraints, and presents some computational results.

IEEE organization defined a standard for floatingpoint arithmetic, used by processing systems, in its directive 754 [1]. This directive encodes floatingpoint numbers using a maximum of 64 bits: 23 bit of fractional as single precision format and 52 bit of fractional as double precision format. The new multimedia terminals require low-power applications; the most important floating-point units (adders and multipliers) represent a significant part of total power wasted by a modern System-OnChip. They might dissipate less power, using a reduced format representation. To verify this possibility, real systems simulate floating - point operations using different formats. In this conference paper, multimedia systems operate in different scenarios: wireless communication and image manipulation.