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Structuring and Automating Hardware Proofs in a HigherOrder TheoremProving Environment
 Formal Methods in System Design
, 1993
"... . In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically design ..."
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Cited by 23 (8 self)
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. In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically designed registertransfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardwarespecific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a generalpurpose, firstorder prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework. Keywords: hardware verification, higherorder logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic com...
Alternative Proof Procedures for FiniteState Machines in HigherOrder Logic
 Higher Order Logic Theorem Proving and Its Applications
, 1993
"... . Verification of digital circuits in higherorder logic often requires the proof of temporal propositional logic formulae. The implementation of decision procedures for this logic or finitestate machines is however not very easy within the HOL system, since it requires the proof of certain fixpoin ..."
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Cited by 6 (5 self)
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. Verification of digital circuits in higherorder logic often requires the proof of temporal propositional logic formulae. The implementation of decision procedures for this logic or finitestate machines is however not very easy within the HOL system, since it requires the proof of certain fixpoint theorems and a creation of a new theory based on it. The main contribution of this paper is to give some alternative proof procedures so that proof tactics can be developed for directly solving these goals. These proof procedures can be classified into two categories. Firstly, a set of easily implementable proof methods which do not use knowledge of fixpoint theorems are given. Since these methods are incomplete, the second category exploits an external program for computing fixpoint lemmata which can then be easily proved in HOL. 1 Introduction The approaches to hardwareverification which are based on the verification of properties of finitestate machines can be fully automated. Recen...
Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path
 In Proceeding of the European Design and Test Conference
, 1994
"... Usually, digital circuits are split up into control and data path as there are specific synthesis methods for controllers and operation units. However, all known approaches to hardware verification which make use of this fact, model the operation unit also as a finitestate machine. This leads to en ..."
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Cited by 4 (2 self)
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Usually, digital circuits are split up into control and data path as there are specific synthesis methods for controllers and operation units. However, all known approaches to hardware verification which make use of this fact, model the operation unit also as a finitestate machine. This leads to enormous space requirements which limit the applicability of these approaches. In order to avoid this, abstraction mechanisms can be used to map boolean tuples onto more complex data types. However, approaches to the verification of generic nbit circuits have considered so far only circuits with simple controllers, such that the verification of only combinational circuits or special cases of sequential circuits is possible. In this paper, we present a new approach to hardware verification which allows the verification of generic circuits with nontrivial controllers. 1 Introduction Over the last few years, a lot of formal approaches to hardware verification have been developed, e.g. equival...
Why Hardware Verification needs more than Model Checking
, 1994
"... . Model checking of temporal propositional logic specifications is a completely automated approach to the verification of digital circuits. One of the main factors that limit the application of such techniques is the size of the problem which can be handled. Many efforts have been undertaken to redu ..."
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. Model checking of temporal propositional logic specifications is a completely automated approach to the verification of digital circuits. One of the main factors that limit the application of such techniques is the size of the problem which can be handled. Many efforts have been undertaken to reduce the space requirements and to speed up the verification algorithms. However, it is shown in this paper, that there are circuits that cannot be specified in model checking approaches in a satisfactory manner, and hence, these circuits cannot be verified by model checking approaches. It is also shown how these circuits can be succinctly specified using higherorder logic, and how they can be verified semiautomatically. 1 Introduction The aim of hardware verification is to show the absence of design errors in digital circuits by proving certain properties. Properties that are to be verified are specified by the designer, and therefore it is mandatory that specifications should be succinct ...
HardwareVerification using First Order BDDs
, 1993
"... Binary decision diagrams (BDDs) are a well known method for representing and comparing boolean functions. Although BDDs are known to be very compact, in all known approaches for hardware verification, BDDbased calculi are restricted to propositional logic. This logic is insufficient for the verific ..."
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Binary decision diagrams (BDDs) are a well known method for representing and comparing boolean functions. Although BDDs are known to be very compact, in all known approaches for hardware verification, BDDbased calculi are restricted to propositional logic. This logic is insufficient for the verification of abstract data types, time abstraction and also for hierarchical verification. In this paper, the lifting of graphs based on shannon expansions and the related binary decision diagrams to first order logic is described and the soundness and correctness theorems are stated. The power of these techniques in the domain of hardware verification is shown by a case study using a hierarchical circuit. Keyword Codes: I.2.3; F.4.1 Keywords: Hardware Verification; Deduction and Theorem Proving; Mathematical Logic 1 Introduction Most automated approaches to hardwareverification are limited to propositional logic or temporal extensions of it (e.g. [BCMD90]), since these logics are decidable. A...