. In this article we present a structured approach to formal hardware verification by modelling circuits at the register-transfer level using a restricted form of higher-order logic. This restricted form of higher-order logic is sufficient for obtaining succinct descriptions of hierarchically designed register-transfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardware-specific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a general-purpose, first-order prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework. Keywords: hardware verification, higher-order logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic com...

. In this paper, we propose a new approach to formal synthesis which focuses on the generation of verification-friendly circuits. Starting from a high-level implementation description, which may result from the application of ususal scheduling and allocation algorithms, hardware is automatically synthesized. The target architecture is based on handshake processes, modules which communicate by a simple synchronizing handshake protocol. Synthesized circuits result from the application of only a few basic operations like synchronization, sequential execution or iteration of base handshake processes. Each process is guided by an abstract theorem that is used to derive proof obligations, to be justified after synthesis. Automation has been achieved to the extend that only those "relevant" proof obligations remain to be proven manually, e.g. theorems for data-dependent loops and lemmata about the used data types. The process-oriented implementation language is enriched by loop invariants. If...

. A methodology for verifying complex circuits is presented, based on a strong coupling of design verification with the hierarchical design process. This goal has been achieved by integrating MEPHISTO, a tool for semi-automated hardware verification, into a commercial design framework. MEPHISTO decomposes the verification goal by a set of hardware-specific proof tactics and provides strategies for synthesizing pre-verified regular components. In case of erroneous implementations, MEPHISTO aids the designer in debugging the circuit by generating a counter model, i.e. input stimuli where specification and implementation behave differently. 1 Introduction To guarantee reliable circuits especially in safety critical applications, and to avoid time consuming and costly redesigns, tools for checking design errors in circuits are mandatory. Usually, this is accomplished by specifying the desired functions and properties of the chip and proving formally that a given implementation behaves a...

Binary decision diagrams (BDDs) are a well known method for representing and comparing boolean functions. Although BDDs are known to be very compact, in all known approaches for hardware verification, BDD-based calculi are restricted to propositional logic. This logic is insufficient for the verification of abstract data types, time abstraction and also for hierarchical verification. In this paper, the lifting of graphs based on shannon expansions and the related binary decision diagrams to first order logic is described and the soundness and correctness theorems are stated. The power of these techniques in the domain of hardware verification is shown by a case study using a hierarchical circuit. Keyword Codes: I.2.3; F.4.1 Keywords: Hardware Verification; Deduction and Theorem Proving; Mathematical Logic 1 Introduction Most automated approaches to hardware-verification are limited to propositional logic or temporal extensions of it (e.g. [BCMD90]), since these logics are decidable. A...

. Model checking of temporal propositional logic specifications is a completely automated approach to the verification of digital circuits. One of the main factors that limit the application of such techniques is the size of the problem which can be handled. Many efforts have been undertaken to reduce the space requirements and to speed up the verification algorithms. However, it is shown in this paper, that there are circuits that cannot be specified in model checking approaches in a satisfactory manner, and hence, these circuits cannot be verified by model checking approaches. It is also shown how these circuits can be succinctly specified using higher-order logic, and how they can be verified semi-automatically. 1 Introduction The aim of hardware verification is to show the absence of design errors in digital circuits by proving certain properties. Properties that are to be verified are specified by the designer, and therefore it is mandatory that specifications should be succinct ...