Reduction of the power dissipation associated with high speed sampling and quantization is a major problem in many applications, including portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers,

Session 2 Mixed-signal modeling Modeling and simulation of a Sigma-Delta digital to analog converter using VHDL-AMS

CMOS sample/hold (S/H) circuits for high sampling rate applications are investigated this report. The work describes a circuit technique called derivative sampling which improves the accuracy of the S/H circuit by reducing the input slew rate contribution to S/H ousput error. It is shown to be applicable to a wide variety of open loop bottom-plate S/H configurations. A simulation strategy which is insensitive to input signal phase-shift and aperture time is also described in conjunction with the S/H circuits studied. Circuit implementation issues are investigated in relation to monolithic interleaved A/D conver-sion. Acknowledgment First of all, I would like to thank my research advisor Professor Rick Carley for his guid-ance and his insightful ideas and discussions. He has given me a lot of freedom to carry out the research at my own pace and let me pick my own focus. I have learned much from him and it has been a pleasure working with him for the past one year and four months. I would also like to thank Professor Dave Allstot for the valuable discussions and for shar-

Dynamic programming is well-known as a powerful modeling technique for dealing with the issue of making optimal decisions sequentially. Many practical problems, such as finding shortest paths in route planning, multi-stage optimal control, can be formulated as special cases of the general sequential decision process. This paper proposes a connectionist network architecture, called the binary relation inference network, which solves a special class of dynamic programming problems in the continuous time. They include the all-pair solutions for a family of closed semiring path problems, such as shortest paths, transitive closure, minimum spanning tree, and minimax path problems. The all-pair inference network specifies a basic and uniform computation of its individual units which then collectively emerge towards a global optimal solution. The computational order in its discrete-time variants, either as synchronous or asynchronous networks, bear a close resemblance to the Floyd-Warshall al...

The study of analog integrated circuits can be carried out at several levels, from the structure and operation of their basic building blocks to the design methodologies. At any of these levels there is a need for tools that allow the influence of design parameters in the behavior of the circuits to be clearly shown to the students.

Feedforward and multiple-feedback - A/D converters offer high-resolution, but are susceptible to instability in the presence of capacitor tolerances in a corresponding switchedcapacitor (SC) hardware implementation. The hitherto - A/D converters are usually based on, a) complementary signal and noise transfer functions, and/or b) unitcircle noise transfer function zeros. This paper is concerned with the development of a novel - A/D converter having, instead, magnitude-squared or magnitude complementary signal and noise transfer functions. The proposed A/D converter exhibits resolution and dynamic range properties similar to those of the existing feedforward and multiplefeedback A/D converters, but oers increased stability performance in the presence of capacitor tolerances in the SC hardware implementation. In addition, the SC hardware implementation of the resulting A/D converter leads to a capacitance spread which is comparable to that of hitherto - A/D converters.

A digital to analog converter for slow control of pixel frontend chip has been designed in a standard 0.35m CMOS technology to prove the effectiveness of the chosen circuit structures for this application. The DAC provides a total output current variation of about 13 A with 8 bits of accuracy (LSB 51nA). The circuit is based on a PMOS current bank, since an " enclosed" NMOS of reasonable size would operate in weak inversion for these current levels and would hence be unsuitable for accurate current sources. The bit value determines whether the corresponding current is switched to the output or sent to ground. The occupied area is about 300m x 300m and total power dissipation is 85W. The results of the test measurements performed on 31 fabricated prototypes show that statistical fluctuations of the output current due to mismatch are negligible compared to the desired accuracy for all the input configurations. Results of X-ray irradiation tests carried out at the CERN facility will be also presented.

I abc The transconductance gain “ gm ” is a function of the Iabc. gm = h1 Iabc for bipolar and weak inversion MOSFETs g m = h 2 [ I abc] 1/2 for MOSFETs in saturation Operational Transconductance Amplifier

Abstract—In this brief, single-path time-interleaved delta-sigma modulators are analyzed and evaluated. It is found that finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the architecture. A hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators is proposed to mitigate the mismatch problem. Index Terms—Analog-to-digital converter (ADC), delta-sigma, oversampling, time-interleaved.

Abstract—We demonstrate a 12-bit 0–3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 m CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0–3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step). Index Terms—ADC, analog-to-digital conversion, delta-sigma modulation, MASH, multi-bit, multistage, oversampling.