We describe an all CMOS variable gain amplifier (VGA) suitable for use in disk drive read channels. The VGA maintains a 3dB bandwidth greater than 85 MHz throughout its gain range. This ensures good phase linearity for data transfer rates of up to 50Mb/s. The VGA provides a 25dB gain variation along an ideal exponential gain to control voltage curve and 30dB of gain control if ideal exponential characteristics is not absolutely necessary. The VGA achieves the necessary exponential gain to control voltage characteristics intrinsically using only MOS transistors as a single unit to reduce power and area consumption. Overall power consumption is less than 10mW for the VGA circuit excluding the off-chip buffer circuits. 1 Introduction The desire for smaller disk drives with reduced power consumption increases the need to integrate the read channel electronics into a single mixed-signal CMOS chip or a set of chips. Variable gain amplifiers (VGA) form an important component of the read ch...

This paper introduces a new architecture for sensor interface circuits using a delta-sigma modulator. The three-level force feedback allows the use of a digital compensator to stabilize the loop. A 3rd-order delta-sigma structure shapes the opamp noise and allows two-chip implementation with high loop gain at low frequencies. 1.

Abstract — Delta-sigma (16) analog-to-digital converters (ADC’s) rely on oversampling to achieve high-resolution. By applying multibit quantization to overcom stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500-kHz 16 ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-"m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date. I.

Abstract—A new fabrication methodology that allows self-alignment of a micromechanical structure to its anchor(s) has been used to achieve vibrating radial-contour mode polysilicon micromechanical disk resonators with resonance frequencies up to 1.156 GHz and measured Q’s at this frequency>2,650 in both vacuum and air. In addition, a 734.6-MHz version has been demonstrated with Q’s of 7,890 and 5,160 in vacuum and air, respectively. For these resonators, self-alignment of the stem to exactly the center of the disk it supports allows balancing of the resonator far superior to that achieved by previous versions (in which separate masks were used to define the disk and stem), allowing the present devices to retain high Q while achieving frequencies in the gigahertz range for the first time. In addition to providing details on the fabrication process, testing techniques, and experimental results, this paper formulates an equivalent electrical circuit model that accurately predicts the performance of these disk resonators. I.

: An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips are available for the CNN Chipset architecture. Time-multiplexed analog routines in the CNN processor require fast and efficient short-time signal storage in an analog buffer. This can be achieved by an extended sample and hold scheme able to address every sample to specific memory locations. Several arrays of capacitors are multiplexed sharing controlling circuitry and I/O buses. The design has the following key parameters: 637 analog memory cells/mm 2 with 0.4% accuracy, 100ns access time and 170ms storage time (within 1% error). 1. Introduction An analog random access memory (ARAM) chip has been designed and integrated in a 0.5m n-well, singlepoly, triple-metal CMOS technology. This circuit is the only missing important part of the chipset of the CNN universal machine [1] [2]. It works as a memory cache for the analog visual microprocessor. In order to take a...

Most of today's video and digital cameras use CCD image sensors, where the electric charge collected by the photodetector array during exposure time is serially shifted out of the sensor chip resulting in slow readout speed and high power consumption. Recently developed CMOS image sensors, by comparison, are read out non-destructively and in a manner similar to a digital memory and can thus be operated at very high frame rates. A CMOS image sensor can also be integrated with other camera functions on the same chip ultimately leading to a single-chip digital camera with very compact size, low power consumption and additional functionality. CMOS image sensors, however, generally su#er from lower dynamic range than CCDs due to their high read noise and non-uniformity. Moreover, as sensor design follows CMOS technology scaling, well capacity will continue to decrease, eventually resulting in unacceptably low SNR.

and Computer Sciences

In this paper we present a high-drivelowpower BiCMOS bu#er ampli#er implemented in a 2#m technology. The class-AB output stage incorporates stacked NPN and compound PMOS#NPN transistors in which the PMOS transistors operate below threshold. Quiescent currentis300#A using a #2:5V supply.Total area is 0:165mm 2 . I.

Charge-Base Capacitance Measurement (CBCM) techniques provide a simple way for measuring the overall parasitic capacitance of on-chip interconnects [1]. However, CBCM suffers from charge injection that limits its accuracy and sensitivity. In this paper we provide extensive simulation and experimental results showing that the effects of charge injection cannot be neglected, nor completely compensated by means of differential measures. To overcome this limitation we propose a modified scheme that makes use of complementary pass-gates with compensating charge injection phenomena. Both the original and the enhanced CBCM techniques have been implemented in 0.18μm and 0.13μm CMOS processes. Comparative experimental results are reported and discussed. 1.

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