structions. Like the "turtle" in the language Logo that can be commanded to draw an image, our language uses an automaton programmed to construct an electrical circuit. The automaton is called a circuit-constructing robot or cc-bot, and the language that programs it is very small and, in its current incarnation, contains only component-placing instructions. The cc-bot language has the desirable property that virtually all possible sequences of instructions result in a valid electrical circuit. This property is important because it greatly limits the "out-of-bounds" regions of the search space containing "illegal" circuits. Thus, an evolutionary algorithm will spend nearly all its time generating valid electrical circuits. While this is a considerable achievement, the ability to generate every possible circuit topology is lost. This is not considered a drawback for the circuit types we investigated since a vast number of topologies and existing circuit designs could be encoded using the

Abstract—Ant colony optimization (ACO) is typically used to search paths through graphs. The concept is based on simulating the behavior of ants in finding paths from the colony to food. Its searching mechanism is applicable for optimizing electric circuits with components, like resistors and capacitors, available in discrete values. In this paper, an extended ACO (eACO) that can search the optimal values of components manufactured in discrete and continuous values is presented. The idea is based on using the orthogonal design method (ODM) to dynamically update the database of the continuous components so that those components will have pseudo-discrete values in the search space. To speed up the optimization process, the ODM performs local search of the best combination around the best ant. The eACO also takes the component tolerances into account in evaluating the fitness value of each ant. The proposed algorithm has been successfully used to optimize the design of a buck regulator. The predicted results have been compared with the published results available in the literature and have also verified with experimental measurements. I.

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As chip complexity explodes and compressed product development cycles relentlessly scale time-tomarket pressures, designers must accomplish more ambitious objectives in less time. For an increasing number of designers, the secret to quickly building highly integrated systems on a chip (SoCs) in a shrinking development cycle lies in the extensive reuse of silicon-proven megafunctions or blocks.

This paper introduces a complete methodology for retargeting of transistor-level circuits to different sets of specifications. By careful integration of the device sizing and layout generation tasks, fully functional designs are generated in a few minutes of CPU time. The methodology is illustrated via the retargeting of a fully-differential Miller-compensated two-stage operational amplifier for a new set of specifications. 1.

This paper introduces a complete methodology for retargeting of analogue blocks to different sets of specifications. By careful integration of the size tuning of devices and layout generation tasks, fully functional designs are generated in a few minutes of CPU time. 1.

One of the basic challenges in the design of large systems is how to reduce time spent to attain the optimal point of the objective function of the design process. The design process itself includes optimization of the structure of the future system, but since this stage is related to an artificial intelligence problem still unresolved, in the general case it is