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Automated Synthesis of Analog Electrical Circuits by Means of Genetic Programming
, 1997
"... The design (synthesis) of analog electrical circuits starts with a highlevel statement of the circuit's desired behavior and requires creating a circuit that satisfies the specified design goals. Analog circuit synthesis entails the creation of both the topology and the sizing (numerical values) of ..."
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Cited by 64 (8 self)
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The design (synthesis) of analog electrical circuits starts with a highlevel statement of the circuit's desired behavior and requires creating a circuit that satisfies the specified design goals. Analog circuit synthesis entails the creation of both the topology and the sizing (numerical values) of all of the circuit's components. The difficulty of the problem of analog circuit synthesis is well known and there is no previously known general automated technique for synthesizing an analog circuit from a highlevel statement of the circuit's desired behavior. This paper presents a single uniform approach using genetic programming for the automatic synthesis of both the topology and sizing of a suite of eight different prototypical analog circuits, including a lowpass filter, a crossover (woofer and tweeter) filter, a source identification circuit, an amplifier, a computational circuit, a timeoptimal controller circuit, a temperaturesensing circuit, and a voltage reference circuit. The problemspecific information required for each of the eight problems is minimal and consists primarily of the number of inputs and outputs of the desired circuit, the types of available components, and a fitness measure that restates the highlevel
Optimal design of a CMOS opamp via geometric programming
 IEEE Transactions on ComputerAided Design
, 2001
"... We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er ..."
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Cited by 51 (10 self)
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We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal tradeo s among competing performance measures such aspower, openloop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeo curves relating performance measures such as power dissipation, unitygain bandwidth, and openloop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a
GPCAD: A Tool for CMOS OpAmp Synthesis
 IN PROCEEDINGS OF THE IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN
, 1998
"... We present a method for optimizing and automating component and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be formulated as posynomial functions of the design variables. As a result, amplifier design problems can be formulated as a g ..."
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Cited by 29 (10 self)
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We present a method for optimizing and automating component and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be formulated as posynomial functions of the design variables. As a result, amplifier design problems can be formulated as a geometric program, a special type of convex optimization problem for which very efficient global optimization methods have recently been developed. The synthesis method is therefore fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected. After briefly
Automated Analog Circuit Synthesis Using a Linear Representation
 Proc. of the Second Int’l Conf on Evolvable Systems: From Biology to Hardware
, 1998
"... We present a method of evolving analog electronic circuits using a linear representation and a simple unfolding technique. While this representation excludes a large number of circuit topologies, it is capable of constructing many of the useful topologies seen in handdesigned circuits. Our syst ..."
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Cited by 27 (6 self)
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We present a method of evolving analog electronic circuits using a linear representation and a simple unfolding technique. While this representation excludes a large number of circuit topologies, it is capable of constructing many of the useful topologies seen in handdesigned circuits. Our system allows circuit size, circuit topology, and device values to be evolved. Using a parallel genetic algorithm we present initial results of our system as applied to two analog filter design problems.
MAELSTROM: Efficient simulationbased synthesis for custom analog cells
 Proc. of the 1999 ACM/IEEE Design Automation Conference
, 1999
"... Analog synthesis tools have failed to migrate into mainstream use primarily because of difficulties in reconciling the simplified models required for synthesis with the industrialstrength simulation environments required for validation. MAELSTROM is a new approach that synthesizes a circuit using t ..."
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Cited by 27 (6 self)
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Analog synthesis tools have failed to migrate into mainstream use primarily because of difficulties in reconciling the simplified models required for synthesis with the industrialstrength simulation environments required for validation. MAELSTROM is a new approach that synthesizes a circuit using the same simulation environment created to validate the circuit. We introduce a novel genetic/ annealing optimizer, and leverage network parallelism to achieve efficient simulatorintheloop analog synthesis. ___________________________ Permission to make digital/hardcopy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.
Structured Design of Microelectromechanical Systems
 in Proceedings of the 1997 Design Automation Conference
"... In order to efficiently design complex microelectromechanical systems (MEMS) having large numbers of multidomain components, a hierarchically structured design approach that is compatible with standard IC design is needed. A graphicalbased schematic, or structural, view is presented as a geometric ..."
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Cited by 17 (3 self)
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In order to efficiently design complex microelectromechanical systems (MEMS) having large numbers of multidomain components, a hierarchically structured design approach that is compatible with standard IC design is needed. A graphicalbased schematic, or structural, view is presented as a geometrically intuitive way to represent MEMS as a set of interconnected lumpedparameter elements. An initial library focuses on suspendedMEMS technology from which inertial sensors and other mechanical mechanisms can be designed. The schematic representation has a simulation interface enabling the designer to simulate the design at the component level. Synthesis of MEMS cells for common topologies provides the system designer with rapid, optimized component layout and associated macromodels. A synthesis module is developed for the popular foldedflexure micromechanical resonator topology. The algorithm minimizes a combination of total layout area and voltage applied to the electromechanical actuators. Synthesis results clearly show the design limits of behavioral parameters such as resonant frequency for a fixed process technology.
Automated Synthesis and Optimization of Robot Configurations
 In Proceedings of the 1998 ASME Design Engineering Technical Conferences
, 1999
"... Robot configuration design is hampered by the lack of established, wellknown design rules, and designers cannot easily grasp the space of possible designs and the impact of all design variables on a robot’s performance. Realistically, a human can only design and evaluate several candidate configura ..."
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Cited by 16 (1 self)
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Robot configuration design is hampered by the lack of established, wellknown design rules, and designers cannot easily grasp the space of possible designs and the impact of all design variables on a robot’s performance. Realistically, a human can only design and evaluate several candidate configurations, though there may be thousands of competitive designs that should be investigated. In contrast, an automated approach to configuration synthesis can create tens of thousands of designs and measure the performance of each one without relying on previous experience or design rules. This thesis creates Darwin2K, an extensible, automated system for robot configuration synthesis. This research focuses on the development of synthesis capabilities required for many robot design problems: a flexible and effective synthesis algorithm, useful simulation capabilities, appropriate representation of robots and their properties, and the ability to accomodate applicationspecific synthesis needs. Darwin2K can synthesize and optimize kinematics, dynamics, structural geometry, actuator selection, and task and control parameters for a wide range of robots.
A Comparison of Dynamic Fitness Schedules for Evolutionary Design of Amplifiers
 in Proceedings of the First NASA/DoD Workshop on Evolvable Hardware
, 1999
"... Highlevel analog circuit design is a complex problem domain in which evolutionary search has recently produced encouraging results. However, little is known about how to best structure evolution for these tasks. The choices of circuit representation, fitness evaluation technique, and genetic operat ..."
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Cited by 13 (7 self)
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Highlevel analog circuit design is a complex problem domain in which evolutionary search has recently produced encouraging results. However, little is known about how to best structure evolution for these tasks. The choices of circuit representation, fitness evaluation technique, and genetic operators clearly have a profound effect on the search process. In this paper, we examine fitness evaluation by comparing the effectiveness of four fitness schedules. Three fitness schedules are dynamic – the evaluation function changes over the course of the run, and one is static. Coevolutionary search is included, and we present a method of evaluating the problem population that is conducive to multiobjective optimization. Twentyfive runs of an analog amplifier design task using each fitness schedule are presented. The results indicate that solution quality is highest with static and coevolving fitness schedules as compared to the other two dynamic schedules. We discuss these results and offer two possible explanations for the observed behavior: retention of useful information, and alignment of problem difficulty with circuit proficiency. 1
ASF: A practical simulationbased methodology for the synthesis of custom analog circuits
 IEEE/ACM Int. Conf. on Computer Aided Design
, 2001
"... Abstract: This paper describes ASF, a novel celllevel analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufacturing process. To manage complexity and timetomarket, SoC designs require a high level of automation and reuse. ..."
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Cited by 9 (1 self)
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Abstract: This paper describes ASF, a novel celllevel analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufacturing process. To manage complexity and timetomarket, SoC designs require a high level of automation and reuse. Digital methodologies are inapplicable to analog IP, which relies on tight control of lowlevel device and circuit properties that vary widely across manufacturing processes. This analog synthesis solution automates these tedious, technology specific aspects of analog design. Unlike previously proposed approaches, ASF extends the prevalent “schematic and SPICE ” methodology used to design analog and mixedsignal circuits. ASF is topology and technology independent and can be easily integrated into a commercial schematic capture design environment. Furthermore, ASF employs a novel numerical optimization formulation that incorporates classical downhill techniques into stochastic search. ASF consistently produces results comparable to expert manual design with 10x fewer candidate solution evaluations than previously published approaches that rely on traditional stochastic optimization methods. I.
Generation of yieldaware pareto surfaces for hierarchical circuit design space exploration
 In DAC
, 2006
"... Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a nondominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulatorinaloop approach. The ..."
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Cited by 9 (0 self)
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Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a nondominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulatorinaloop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yieldaware pareto fronts. We show experimental results for both the nominal and yieldaware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yieldaware pareto fronts in approximately 56 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yieldaware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop.