An automatic synthesis tool for CMOS op amps (OPASYN) has been developed. The program starts from one of a number of op amp circuits and proceeds to optimize various device sizes and bias currents to meet a given set of design specifications. Because it uses analytic circuit models in its inner optimization loop, it can search efficiently through a large part of the possible solution space. The program has a SPICE interface that automatically performs circuit simulations for the candidate solutions to verify the results of the synthesis and optimization procedure. The simulation results are also used to fine-tune the analytic circuit descriptions in the database. OPASYN has been implemented in Franz Lisp and demonstrated for three different basic circuits with a conventional 3 µm process and a more advanced 1.5 µm process. Experiments have shown that OPASYN quickly produces practical designs which will meet reasonable design objectives. 1.

This paper addresses the following question: how to ensure that a complex analogue integrated circuit is easily testable? There are two aspects of this problem: design of the circuit and development of the tests. We review some solutions to the testing problems recently proposed in the literature. The example of testing fuzzy logic controller is used to demonstrate how the problem of testing of a complex analogue circuit can be approached. The circuit level sensitivity-based approach is commonly used for analysis of possible faulty behaviour of an analogue circuit. We propose an additional method based on statistical analysis done on physical design level which allows to predict the parametric faults more realistically. 1. INTRODUCTION Testing of analogue circuits and mixed-mode circuits has recently gained much attention in the literature. The subject covers testing of many different classes of circuits such as A/D and D/A converters, PLLs, amplifiers, TV circuits, telecommunicati...

This thesis describes the design of a simultaneous bidirectional MOS driver on a 0:8m CMOS process. Simulation results show that the driver allow simultaneous bidirectional digital signalling over the same pin at 400 MBits per second. The driver operates with current mode signals to isolate the digital signal from power and ground noise. A small chip with testing circuitry was implemented on a 1:2m CMOS process. Thesis Supervisor: William J. Dally Title: Associate Professor The Design of a High Performance Simultaneous Bidirectional MOS Driver by Kin Hong Kan Submitted to the Department of Electrical Engineering and Computer Science on May 7, 1993, in partial fulfillment of the requirements for the degree of Bachelor of Science in Computer Science and Engineering Abstract This thesis describes the design of a simultaneous bidirectional MOS driver on a 0:8m CMOS process. Simulation results show that the driver allow simultaneous bidirectional digital signalling over the same...

! Performance of a basic two-stage OP-AMP! Design issues, constraints, tradeoffs discussed! PART II:! Alternative architectures for improved performance! Design of output stagesIntroduction! Relevance of OP AMP design! Designing OP AMPS for single-chip

A custom monolithic circuit has been developed for the Time Expansion Chamber (TEC) of the PHENIX detector at the Relativistic Heavy Ion Collider (RHIC) at Brookhaven National Laboratory (BNL). This detector identifies particles by sampling their ionization energy loss (dE/dx) over a 3 cm drift space and by detecting associated transition radiation (TR) photons. The requirement of being simultaneously sensitive to dE/dx and TR events requires a dual-gain system. We have developed a compact solution featuring an octal preamplifier/shaper (P/S) IC with a split gain stage. The circuit, fabricated in 1.2 m CMOS process, incorporates a trans-impedance preamplifier and a 70 ns unipolar CR-RC 4 shaper with ion tail compensation and active DC offset cancellation. Digitally selectable gain, peaking time, and tail cancellation as well as channel-by-channel charge injection and disable can be configured in the system via a 3-wire interface. The 3.5 x 5 mm 2 die is packaged in a fine-pitch 64p...

A hybrid architecture for neural coprocessing is presented. A fixed set of analog multipliers and capacitors (analog memory) emulates Multilayer Perceptrons through digitally-controlled multiplexing. Parallelism is partially preserved, then, without direct analog implementation of the whole structure. Details of system VLSI implementation are given, along with simulation results that validate system cells design. 1.

The papers presents a 1V rail to rail operational amplifier that has been used as a unity gain buffer in the sample and hold circuit for 1V 10 bit 1Msps pipeline ADC in 0.18µm technology. An open loop architecture is chosen for the implementation of sample and hold circuit. The transmission gate switch is used in the sample and hold circuit for reducing the effect of channel charge injection and clock feed through. Also, the transmission gate switch offers a low resistance as compared to pMOS or nMOS switches switches. The sample and hold circuit speed up to 1Msps has been achieved. Keywords: Rail to Rail,SNR, amplifier ADC. Sample and Hold circuits are heart of any Analog to