Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs--AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic tranceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of futur...

This paper presents Chatoyant, a tool for simulation and analysis of heterogeneous free space optoelectronic architectures. It is capable of modeling digital and analog electronic and optical signal propagation with mechanical tolerancing at the system level. We present models for a variety of optoelectronic devices, and results that demonstrate the system’s ability to predict the effects of various component parameters, such as detector geometry, and system parameters, such as alignment tolerances, on system performance measures, such as bit error rate. 1.

Chatoyant is a tool for the simulation and the analysis of heterogeneous free-space optoelectronic architectures. It is capable of modeling digital and analog electronic and optical signal propagation with mechanical tolerancing at the system level. We present models for a variety of optoelectronic devices and results that demonstrate the system’s ability to predict the effects of various component parameters, such as detector geometry, and system parameters, such as alignment tolerances, on system-performance measures, such as the bit-error rate. © 1998 Optical Society of America OCIS codes: 200.0200, 220.0220, 220.4830, 250.0250. 1.

...................................................................................................................................... viii List of publications .......................................................................................................................ix Chapter 1: Introduction..................................................................................................................1 1.1 Scope and overall research contribution..............................................................................1 1.2 Motivation............................................................................................................................2 1.2.1 The interconnect problem .............................................................................................2 1.2.2 Capabilities and limitations of electrical interconnects................................................4 1.2.3 Advantages of optical interconnects ......................................

The evolution of integrated circuit technology is causing system designs to move towards communication-based architectures. However, metallic interconnect networks can be very costly in terms of power and silicon area and can thus become a bottleneck in system on chip design. Integrated optical interconnect has been identified by the ITRS as a potential solution to overcome predicted interconnect limitations. This paper firstly presents the technological and device aspects of integrated optical interconnect for on-chip data transport. The second part of the paper concentrates on simulation-based quantitative comparisons of electrical to optical interconnect at the physical link level, and it is demonstrated that a ten-fold reduction in interconnect power consumption can be achieved through the use of optics. Finally some more advanced concepts are introduced in the form of optical networks on chip.